[Qemu-commits] [qemu/qemu] a575d9: target-ppc/fpu_helper: Fix efscmp* instructions ha...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: a575d9ab2e1cdfe61bc5cc8d94bd96e2adda5b44
      
https://github.com/qemu/qemu/commit/a575d9ab2e1cdfe61bc5cc8d94bd96e2adda5b44
  Author: Talha Imran <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  target-ppc/fpu_helper: Fix efscmp* instructions handling

With specification at hand from the reference manual from Freescale
http://cache.nxp.com/files/32bit/doc/ref_manual/SPEPEM.pdf , I have found a fix
to efscmp* instructions handling in QEMU.

efscmp* instructions in QEMU set crD (Condition Register nibble) values as
(0b0100 << 2) = 0b10000 (consider the HELPER_SINGLE_SPE_CMP macro which left
shifts the value returned by efscmp* handler by 2 bits). A value of 0b10000 is
not correct according the to the reference manual.

The reference manual expects efscmp* instructions to return a value of 0bx1xx.
Please find attached a patch which disables left shifting in
HELPER_SINGLE_SPE_CMP macro. This macro is used by efscmp* and efstst*
instructions only. efstst* instruction handlers, in turn, call efscmp* handlers
too.

*Explanation:*
Traditionally, each crD (condition register nibble) consist of 4 bits, which is
set by comparisons as follows:
crD = W X Y Z
where
W = Less than
X = Greater than
Y = Equal to

However, efscmp* instructions being a special case return a binary result.
(efscmpeq will set the crD = 0bx1xx iff when op1 == op2 and 0bx0xx otherwise;
i.e. there is no notion of different crD values based on Less than, Greater
than and Equal to).

This effectively means that crD will store a "Greater than" comparison result
iff efscmp* instruction comparison is TRUE. Compiler exploits this feature by
checking for "Branch if Less than or Equal to" (ble instruction) OR "Branch if
Greater than" (bgt instruction) for Branch if FALSE OR Branch if TRUE
respectively after an efscmp* instruction. This can be seen in a assembly code
snippet below:

27          if (__real__ x != 3.0f || __imag__ x != 4.0f)
10000498:   lwz r10,8(r31)
1000049c:   lis r9,16448
100004a0:   efscmpeq cr7,r10,r9
100004a4:   ble- cr7,0x100004b8 <bar+60>  //jump to abort() call
100004a8:   lwz r10,12(r31)
100004ac:   lis r9,16512
100004b0:   efscmpeq cr7,r10,r9
100004b4:   bgt- cr7,0x100004bc <bar+64>  //skip abort() call
28            abort ();
100004b8:   bl 0x10000808 <abort>

Signed-off-by: Talha Imran <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 44f2e6c10eb2bf5dc3e36372ed574f71e80dba30
      
https://github.com/qemu/qemu/commit/44f2e6c10eb2bf5dc3e36372ed574f71e80dba30
  Author: Bharata B Rao <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M include/sysemu/kvm.h
    M kvm-all.c

  Log Message:
  -----------
  kvm: API to obtain max supported mem slots

Introduce kvm_get_max_memslots() API that can be used to obtain the
maximum number of memslots supported by KVM.

Signed-off-by: Bharata B Rao <address@hidden>
Acked-by: Paolo Bonzini <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 705124ea6dca3ebfa13afddac9ce9475caf981a6
      
https://github.com/qemu/qemu/commit/705124ea6dca3ebfa13afddac9ce9475caf981a6
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M include/migration/vmstate.h

  Log Message:
  -----------
  vmstate: Define VARRAY with VMS_ALLOC

This allows dynamic allocation for migrating arrays.

Already existing VMSTATE_VARRAY_UINT32 requires an array to be
pre-allocated, however there are cases when the size is not known in
advance and there is no real need to enforce it.

This defines another variant of VMSTATE_VARRAY_UINT32 with WMS_ALLOC
flag which tells the receiving side to allocate memory for the array
before receiving the data.

The first user of it is a dynamic DMA window which existence and size
are totally dynamic.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: df7625d422a61acbdb9b10a5b4f3bd576ec94c50
      
https://github.com/qemu/qemu/commit/df7625d422a61acbdb9b10a5b4f3bd576ec94c50
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M hw/ppc/spapr_iommu.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_vio.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr_iommu: Introduce "enabled" state for TCE table

Currently TCE tables are created once at start and their sizes never
change. We are going to change that by introducing a Dynamic DMA windows
support where DMA configuration may change during the guest execution.

This changes spapr_tce_new_table() to create an empty zero-size IOMMU
memory region (IOMMU MR). Only LIOBN is assigned by the time of creation.
It still will be called once at the owner object (VIO or PHB) creation.

This introduces an "enabled" state for TCE table objects, some
helper functions are added:
- spapr_tce_table_enable() receives TCE table parameters, stores in
sPAPRTCETable and allocates a guest view of the TCE table
(in the user space or KVM) and sets the correct size on the IOMMU MR;
- spapr_tce_table_disable() disposes the table and resets the IOMMU MR
size; it is made public as the following DDW code will be using it.

This changes the PHB reset handler to do the default DMA initialization
instead of spapr_phb_realize(). This does not make differenct now but
later with more than just one DMA window, we will have to remove them all
and create the default one on a system reset.

No visible change in behaviour is expected except the actual table
will be reallocated every reset. We might optimize this later.

The other way to implement this would be dynamically create/remove
the TCE table QOM objects but this would make migration impossible
as the migration code expects all QOM objects to exist at the receiver
so we have to have TCE table objects created when migration begins.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a26fdf393404e96b51bec5db9ed6bd54ab6eab85
      
https://github.com/qemu/qemu/commit/a26fdf393404e96b51bec5db9ed6bd54ab6eab85
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M hw/ppc/spapr_iommu.c
    M include/hw/ppc/spapr.h
    M trace-events

  Log Message:
  -----------
  spapr_iommu: Migrate full state

The source guest could have reallocated the default TCE table and
migrate bigger/smaller table. This adds reallocation in post_load()
if the default table size is different on source and destination.

This adds @bus_offset, @page_shift to the migration stream as
a subsection so when DDW is added, migration to older machines will
still be possible. As @bus_offset and @page_shift are not used yet,
this makes no change in behavior.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b4b6eb771a5c2eec47fd87ea28c499a5aa4b6db2
      
https://github.com/qemu/qemu/commit/b4b6eb771a5c2eec47fd87ea28c499a5aa4b6db2
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M hw/ppc/spapr_iommu.c
    M hw/ppc/spapr_pci.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr_iommu: Add root memory region

We are going to have multiple DMA windows at different offsets on
a PCI bus. For the sake of migration, we will have as many TCE table
objects pre-created as many windows supported.
So we need a way to map windows dynamically onto a PCI bus
when migration of a table is completed but at this stage a TCE table
object does not have access to a PHB to ask it to map a DMA window
backed by just migrated TCE table.

This adds a "root" memory region (UINT64_MAX long) to the TCE object.
This new region is mapped on a PCI bus with enabled overlapping as
there will be one root MR per TCE table, each of them mapped at 0.
The actual IOMMU memory region is a subregion of the root region and
a TCE table enables/disables this subregion and maps it at
the specific offset inside the root MR which is 1:1 mapping of
a PCI address space.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: acf1b6dd22ef8ccd5431e933706f12ce643f6cf0
      
https://github.com/qemu/qemu/commit/acf1b6dd22ef8ccd5431e933706f12ce643f6cf0
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr_pci: Reset DMA config on PHB reset

LoPAPR dictates that during system reset all DMA windows must be removed
and the default DMA32 window must be created so does the patch.

At the moment there is just one window supported so no change in
behaviour is expected.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b3162f22cb3cbca73d4c90b936dbadff6954e2f6
      
https://github.com/qemu/qemu/commit/b3162f22cb3cbca73d4c90b936dbadff6954e2f6
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M hw/ppc/spapr_pci.c
    M include/hw/pci-host/spapr.h

  Log Message:
  -----------
  spapr_pci: Add and export DMA resetting helper

This will be later used by the "ibm,reset-pe-dma-window" RTAS handler
which resets the DMA configuration to the defaults.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 71c9a3dd04e462c2d07c7e343de137ae6f9a96aa
      
https://github.com/qemu/qemu/commit/71c9a3dd04e462c2d07c7e343de137ae6f9a96aa
  Author: Bharata B Rao <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Increase hotpluggable memory slots to 256

KVM now supports 512 memslots on PowerPC (earlier it was 32). Allow half
of it (256) to be used as hotpluggable memory slots.

Instead of hard coding the max value, use the KVM supplied value if KVM
is enabled. Otherwise resort to the default value of 32.

Signed-off-by: Bharata B Rao <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1ea1eefcbbcbea91ab295bd5c8c5330d1f458174
      
https://github.com/qemu/qemu/commit/1ea1eefcbbcbea91ab295bd5c8c5330d1f458174
  Author: Bharata B Rao <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Introduce pseries-2.7 machine type

Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 932ccbdd48cea5b86f895bdc7d6b409d24aa81cd
      
https://github.com/qemu/qemu/commit/932ccbdd48cea5b86f895bdc7d6b409d24aa81cd
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Better figure out if processor has HV mode

We use an env. flag which is set to the initial value of MSR_HVB in
the msr_mask. We also adjust the POWER8 mask to set SHV.

Also use this to adjust ctx.hv so that it is *set* when the processor
doesn't have an HV mode (970 with Apple mode for example), thus enabling
hypervisor instructions/SPRs.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: ctx.hv used to be defined only for the hypervisor kernel
      (HV=1|PR=0). It is now defined also when PR=1 and conditions are
      fixed accordingly.
      stripped unwanted tabs.]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1c953ba57ada0a8694abb5db4bc618dde35a4618
      
https://github.com/qemu/qemu/commit/1c953ba57ada0a8694abb5db4bc618dde35a4618
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/excp_helper.c
    M target-ppc/helper_regs.h

  Log Message:
  -----------
  ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV

This helper is only used by the various instructions that can alter
MSR and not interrupts. Add a comment to that effect to the interrupt
code as well in case somebody wants to change this

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1c7336c5d1f720e8d320cb36f9d747ad24663e0d
      
https://github.com/qemu/qemu/commit/1c7336c5d1f720e8d320cb36f9d747ad24663e0d
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: fix hrfid, tlbia and slbia privilege

commit 74693da98894 ('ppc: tlbie, tlbia and tlbisync are HV only')
introduced some extra checks on the instruction privilege. slbia was
changed wrongly and hrfid, tlbia were forgotten.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 679dd415bb36aec5376e74454408ab70b2066e59
      
https://github.com/qemu/qemu/commit/679dd415bb36aec5376e74454408ab70b2066e59
  Author: Markus Armbruster <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr_pci: Drop cannot_instantiate_with_device_add_yet=false

It's become redundant since it was added in commit 09aa9a5 "spapr-pci:
enable adding PHB via -device".

Cc: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9207113dcc49cb742de0ec8a96d9373efa54cc88
      
https://github.com/qemu/qemu/commit/9207113dcc49cb742de0ec8a96d9373efa54cc88
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/mmu_helper.c

  Log Message:
  -----------
  target-ppc: fixup bitrot in mmu_helper.c debug statements

This fixes compilation of mmu_helper.c when all of the debug #defines at
the start of the file are enabled.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ddd495e5e3a70dfe30386f649aad1b2c9469a4d5
      
https://github.com/qemu/qemu/commit/ddd495e5e3a70dfe30386f649aad1b2c9469a4d5
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M hw/ide/macio.c

  Log Message:
  -----------
  macio: use DMA memory interface for non-block ATAPI transfers

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 88655881335d3c842020418fdec7f04ecb3a50ae
      
https://github.com/qemu/qemu/commit/88655881335d3c842020418fdec7f04ecb3a50ae
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M hw/misc/macio/mac_dbdma.c

  Log Message:
  -----------
  dbdma: use DMA memory interface for memory accesses

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f5d9c1089f0136c2aadf51389e93a94d517e430f
      
https://github.com/qemu/qemu/commit/f5d9c1089f0136c2aadf51389e93a94d517e430f
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/helper_regs.h

  Log Message:
  -----------
  ppc: Properly tag the translation cache based on MMU mode

We used to always flush the TLB when changing relocation mode in
MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data).

We don't anymore since we have split mmu_idx for instruction and data.

However, since we hard code the mmu_idx in the translated code, we
now need to also make sure MSR:IR and MSR:DR are part of the hflags
used to tag translated code, so that we use different translated
code for different MMU settings.

Darwin gets hurt by this problem.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3dcfb74fd4e4ab31508c80e6965a0cd477510234
      
https://github.com/qemu/qemu/commit/3dcfb74fd4e4ab31508c80e6965a0cd477510234
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/mmu_helper.c

  Log Message:
  -----------
  ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors

The processor only uses some bits of the address and invalidates an
entire congruence class. Some OSes such as Darwin and HelenOS take
advantage of this and occasionally invalidate the entire TLB by just
doing a series of 64 consecutive tlbie for example.

Our code tries to be too smart here only invalidating a segment
congruence class (ie, allowing more address bits to be relevant
in the invalidation), this fails miserably on those OSes.

Instead don't bother, do like ppc64 and blow the whole tlb when tlbie
is executed.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c5a8d8f32d90058995334cfd9292ed1b98c76971
      
https://github.com/qemu/qemu/commit/c5a8d8f32d90058995334cfd9292ed1b98c76971
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/helper_regs.h
    M target-ppc/mmu_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode

This ports the existing 64-bit mechanism to 32-bit, thus series
of 64 tlbie's followed by a sync like some versions of Darwin
(ab)use will result in a single flush.

We apply a pending flush on any sync instruction though, as Darwin
doesn't use tlbsync on non-SMP systems.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8eb0f5637219820bfda8082296e1d3e39132d8de
      
https://github.com/qemu/qemu/commit/8eb0f5637219820bfda8082296e1d3e39132d8de
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: POWER7 had ACOP and PID registers

We only had them on POWER8, add them to POWER7 as well

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: dfdd3e43620a6cd4f2be31da5a257c84a16fc000
      
https://github.com/qemu/qemu/commit/dfdd3e43620a6cd4f2be31da5a257c84a16fc000
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: POWER7 has lq/stq instructions and stq need to check ISA

The PPC_64BX instruction flag is used for a couple of newer
instructions currently on POWER8 but our implementation for
them works for POWER7 too (and already does the proper checking
of what is permitted) with one exception: stq needs to check
the ISA version.

This fixes the latter and add the instructions to POWER7

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5e31867fbdefca66fe29f02c59b950c716c2ce64
      
https://github.com/qemu/qemu/commit/5e31867fbdefca66fe29f02c59b950c716c2ce64
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Fix mtmsr decoding

We had code to handle the L bit in the opcode but we didn't
allow it in the decode mask.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2f9254d96450e3269a029b941f0a5bc60f2dfd16
      
https://github.com/qemu/qemu/commit/2f9254d96450e3269a029b941f0a5bc60f2dfd16
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Fix slbia decode

Since at least the 2.05 architecture, the slbia instruction takes an
IH field in the opcode to provide some control on the effect of the
slbia on the ERATs (level-1 TLB).

We can safely ignore it as we always flush the whole qemu TLB but
we should allow the bits in the decode.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c76c22d51d347fc65d8d1b1e6e007cd2886e6313
      
https://github.com/qemu/qemu/commit/c76c22d51d347fc65d8d1b1e6e007cd2886e6313
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/mmu-hash64.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Add missing slbfee. instruction on ppc64 BookS processors

Used to lookup SLB entries by address, for some reason it was missing.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4d6a0680fa425230748a2d91d81be9afe050eeb3
      
https://github.com/qemu/qemu/commit/4d6a0680fa425230748a2d91d81be9afe050eeb3
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Do not take exceptions on unknown SPRs in privileged mode

The architecture specifies that mtspr/mfspr on an unknown SPR number
should act as a nop in privileged mode.

I haven't removed the warning however as it can be useful for
diagnosing.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0601d6a4112a5b0333d2348aa2c3465cc0075ec6
      
https://github.com/qemu/qemu/commit/0601d6a4112a5b0333d2348aa2c3465cc0075ec6
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-07 (Tue, 07 Jun 2016)

  Changed paths:
    M hw/ide/macio.c
    M hw/misc/macio/mac_dbdma.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_iommu.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_vio.c
    M include/hw/pci-host/spapr.h
    M include/hw/ppc/spapr.h
    M include/migration/vmstate.h
    M include/sysemu/kvm.h
    M kvm-all.c
    M target-ppc/cpu.h
    M target-ppc/excp_helper.c
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/helper_regs.h
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu_helper.c
    M target-ppc/translate.c
    M target-ppc/translate_init.c
    M trace-events

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160607' into 
staging

ppc patch queue for 2016-05-31

Latest patch queue for ppc.  Several significant things in here:
  * A bunch of patches from BenH fixing things in TCG
     - This should fix several regressions introduced by recent
       patches for better HV mode support
     - It also fixes some other bugs discovered along the way
  * Some fixes and cleanups for Mac machine types from Marc
    Cave-Ayland
  * Preliminary patches towards dynamic DMA window support from Alexey
    Kardashevskiy
      - This includes a patch to migration code code
  * Increase number of hotpluggable memory slots
      - Includes a change to KVM generic code, ACKed by Paolo
  * Another TCG fix for an SPE instruction

# gpg: Signature made Tue 07 Jun 2016 11:46:57 BST
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.7-20160607: (26 commits)
  ppc: Do not take exceptions on unknown SPRs in privileged mode
  ppc: Add missing slbfee. instruction on ppc64 BookS processors
  ppc: Fix slbia decode
  ppc: Fix mtmsr decoding
  ppc: POWER7 has lq/stq instructions and stq need to check ISA
  ppc: POWER7 had ACOP and PID registers
  ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode
  ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors
  ppc: Properly tag the translation cache based on MMU mode
  dbdma: use DMA memory interface for memory accesses
  macio: use DMA memory interface for non-block ATAPI transfers
  target-ppc: fixup bitrot in mmu_helper.c debug statements
  spapr_pci: Drop cannot_instantiate_with_device_add_yet=false
  ppc: fix hrfid, tlbia and slbia privilege
  ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
  ppc: Better figure out if processor has HV mode
  spapr: Introduce pseries-2.7 machine type
  spapr: Increase hotpluggable memory slots to 256
  spapr_pci: Add and export DMA resetting helper
  spapr_pci: Reset DMA config on PHB reset
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/76462405809d...0601d6a4112a