qemu-commits
[Top][All Lists]
Advanced
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] 6b0407: target-arm: Add support for PMU regis

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 6b0407: target-arm: Add support for PMU register PMSELR_EL...
Date: Mon, 13 Feb 2017 01:30:10 -0800 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6b0407805d46bbeba70f4be426285d0a0e669750
      
https://github.com/qemu/qemu/commit/6b0407805d46bbeba70f4be426285d0a0e669750
  Author: Wei Huang <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target-arm: Add support for PMU register PMSELR_EL0

This patch adds support for AArch64 register PMSELR_EL0. The existing
PMSELR definition is revised accordingly.

Signed-off-by: Wei Huang <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
[PMM: Moved #ifndef CONFIG_USER_ONLY to cover new regdefs]
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fdb8665672ded05f650d18f8b62d5c8524b4385b
      
https://github.com/qemu/qemu/commit/fdb8665672ded05f650d18f8b62d5c8524b4385b
  Author: Wei Huang <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0

In order to support Linux perf, which uses PMXEVTYPER register,
this patch adds read/write access support for PMXEVTYPER. The access
is CONSTRAINED UNPREDICTABLE when PMSELR is not 0x1f. Additionally
this patch adds support for PMXEVTYPER_EL0.

Signed-off-by: Wei Huang <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e6ec54571e424bb1d6e50e32fe317c616cde3e05
      
https://github.com/qemu/qemu/commit/e6ec54571e424bb1d6e50e32fe317c616cde3e05
  Author: Wei Huang <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target-arm: Add support for PMU register PMINTENSET_EL1

This patch adds access support for PMINTENSET_EL1.

Signed-off-by: Wei Huang <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d6f02ce3b8a43ddd8f83553fe754a34b26fb273f
      
https://github.com/qemu/qemu/commit/d6f02ce3b8a43ddd8f83553fe754a34b26fb273f
  Author: Wei Huang <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M hw/arm/virt.c
    M target/arm/cpu.c
    M target/arm/helper.c

  Log Message:
  -----------
  target-arm: Enable vPMU support under TCG mode

This patch contains several fixes to enable vPMU under TCG mode. It
first removes the checking of kvm_enabled() while unsetting
ARM_FEATURE_PMU. With it, the .pmu option can be used to turn on/off vPMU
under TCG mode. Secondly the PMU node of DT table is now created under TCG.
The last fix is to disable the masking of PMUver field of ID_AA64DFR0_EL1.

Signed-off-by: Wei Huang <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 054bb7b215d621d7b3bba16f40bf3291ef4f430b
      
https://github.com/qemu/qemu/commit/054bb7b215d621d7b3bba16f40bf3291ef4f430b
  Author: Alexander Graf <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M hw/arm/vexpress.c
    M hw/arm/virt.c

  Log Message:
  -----------
  target-arm: Declare virtio-mmio as dma-coherent in dt

QEMU emulated hardware is always dma coherent with its guest. We do
annotate that correctly on the PCI host controller, but left out
virtio-mmio.

Recent kernels have started to interpret that flag rather than take
dma coherency as granted with virtio-mmio. While that is considered
a kernel bug, as it breaks previously working systems, it showed that
our dt description is incomplete.

This patch adds the respective marker that allows guest OSs to evaluate
that our virtio-mmio devices are indeed cache coherent.

Signed-off-by: Alexander Graf <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Reviewed-by: Ard Biesheuvel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 76266d9913961922415ce46b628e4ad706a1ef08
      
https://github.com/qemu/qemu/commit/76266d9913961922415ce46b628e4ad706a1ef08
  Author: Alexander Graf <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M hw/arm/virt-acpi-build.c

  Log Message:
  -----------
  hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI

Virtio-mmio devices can directly access guest memory and do so in cache
coherent fashion. Tell the guest about that fact when it's using ACPI.

Signed-off-by: Alexander Graf <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Reviewed-by: Ard Biesheuvel <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3b5c492b1c728f90b17520be74c4d74c9797c55c
      
https://github.com/qemu/qemu/commit/3b5c492b1c728f90b17520be74c4d74c9797c55c
  Author: Alexander Graf <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M hw/arm/virt-acpi-build.c

  Log Message:
  -----------
  hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI

Fw-cfg recently learned how to directly access guest memory and does so in
cache coherent fashion. Tell the guest about that fact when it's using ACPI.

Signed-off-by: Alexander Graf <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Reviewed-by: Ard Biesheuvel <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 14efdb5cb3540d5ada51b81b70ec18ce95ae1642
      
https://github.com/qemu/qemu/commit/14efdb5cb3540d5ada51b81b70ec18ce95ae1642
  Author: Alexander Graf <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Declare fwcfg as dma cache coherent in dt

Fw-cfg recently learned how to directly access guest memory and does so in
cache coherent fashion. Tell the guest about that fact when it's using DT.

Signed-off-by: Alexander Graf <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Reviewed-by: Ard Biesheuvel <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0c7209bee805bcc974cf16cd567c8865db5d1ce5
      
https://github.com/qemu/qemu/commit/0c7209bee805bcc974cf16cd567c8865db5d1ce5
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: check for negative values returned by blk_getlength()

write_boot_rom() does not check for negative values. This is more a
problem for coverity than the actual code as the size of the flash
device is checked when the m25p80 object is created. If there is
anything wrong with the backing file, we should not even reach that
path.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 93bf276d5f47c7b743d40a92b881c53acc882525
      
https://github.com/qemu/qemu/commit/93bf276d5f47c7b743d40a92b881c53acc882525
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: remove useless comment on controller segment size

The flash devices used for the FMC controller (BMC firmware) are well
defined for each Aspeed machine and are all smaller than the default
mapping window size, at least for CE0 which is the chip the SoC boots
from.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1a6d4fc27d75839b6a0325ef258560fded6ec7d9
      
https://github.com/qemu/qemu/commit/1a6d4fc27d75839b6a0325ef258560fded6ec7d9
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: handle dummies only in fast read mode

HW works fine in normal read mode with dummy bytes being set. So let's
check this case to not transfer bytes.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b4cc583f0285a2e1e78621dfba142f00ca47414a
      
https://github.com/qemu/qemu/commit/b4cc583f0285a2e1e78621dfba142f00ca47414a
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: use a modulo to check segment limits

The size of a segment is not necessarily a power of 2.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6311b19b5c650388745aafe1269489bd5afe4f2d
      
https://github.com/qemu/qemu/commit/6311b19b5c650388745aafe1269489bd5afe4f2d
  Author: Peter Maydell <address@hidden>
  Date:   2017-02-10 (Fri, 10 Feb 2017)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/vexpress.c
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M hw/ssi/aspeed_smc.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170210' 
into staging

target-arm queue:
 * aspeed: minor fixes
 * virt: declare fwcfg and virtio-mmio as DMA coherent in DT & ACPI
 * arm: enable basic TCG emulation of PMU for AArch64

# gpg: Signature made Fri 10 Feb 2017 18:06:30 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170210:
  aspeed/smc: use a modulo to check segment limits
  aspeed/smc: handle dummies only in fast read mode
  aspeed: remove useless comment on controller segment size
  aspeed: check for negative values returned by blk_getlength()
  hw/arm/virt: Declare fwcfg as dma cache coherent in dt
  hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI
  hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI
  target-arm: Declare virtio-mmio as dma-coherent in dt
  target-arm: Enable vPMU support under TCG mode
  target-arm: Add support for PMU register PMINTENSET_EL1
  target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0
  target-arm: Add support for PMU register PMSELR_EL0

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/98b2faeaee96...6311b19b5c65
reply via email to
[Prev in Thread] Current Thread [Next in Thread]