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[Qemu-commits] [qemu/qemu] 0b6a03: linux-user/aarch64: Reset btype for s
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 0b6a03: linux-user/aarch64: Reset btype for signals |
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Date: |
Thu, 29 Oct 2020 07:30:28 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 0b6a03c044b6b0b09ad590c0d8b1bc60f12b9612
https://github.com/qemu/qemu/commit/0b6a03c044b6b0b09ad590c0d8b1bc60f12b9612
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M linux-user/aarch64/signal.c
Log Message:
-----------
linux-user/aarch64: Reset btype for signals
The kernel sets btype for the signal handler as if for a call.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: be5d6f4884021208ae0e73379c83e51500ad3a8d
https://github.com/qemu/qemu/commit/be5d6f4884021208ae0e73379c83e51500ad3a8d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M include/exec/cpu-all.h
M linux-user/mmap.c
M linux-user/syscall_defs.h
M target/arm/cpu.h
M target/arm/translate-a64.c
Log Message:
-----------
linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI
Transform the prot bit to a qemu internal page bit, and save
it in the page tables.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 069175bfd821a9ef16b0110b92b2b6116f981fc0
https://github.com/qemu/qemu/commit/069175bfd821a9ef16b0110b92b2b6116f981fc0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M include/elf.h
Log Message:
-----------
include/elf: Add defines related to GNU property notes for AArch64
These are all of the defines required to parse
GNU_PROPERTY_AARCH64_FEATURE_1_AND, copied from binutils.
Other missing defines related to other GNU program headers
and notes are elided for now.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2b323087b546553408c69dd6e92c5d492a49b003
https://github.com/qemu/qemu/commit/2b323087b546553408c69dd6e92c5d492a49b003
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user/elfload: Avoid leaking interp_name using GLib memory API
Fix an unlikely memory leak in load_elf_image().
Fixes: bf858897b7 ("linux-user: Re-use load_elf_image for the main binary.")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-5-richard.henderson@linaro.org
Message-Id: <20201003174944.1972444-1-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e5eaf570a3df577e09347ba071841caec8b61372
https://github.com/qemu/qemu/commit/e5eaf570a3df577e09347ba071841caec8b61372
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user/elfload: Fix coding style in load_elf_image
Fixing this now will clarify following patches.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-6-richard.henderson@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4d9d535a8a52bf9ccc2c325b88498b35b6cc579d
https://github.com/qemu/qemu/commit/4d9d535a8a52bf9ccc2c325b88498b35b6cc579d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user/elfload: Adjust iteration over phdr
The second loop uses a loop induction variable, and the first
does not. Transform the first to match the second, to simplify
a following patch moving code between them.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-7-richard.henderson@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8a1a5274c9395e2d92aaf6126379f58804a82aca
https://github.com/qemu/qemu/commit/8a1a5274c9395e2d92aaf6126379f58804a82aca
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user/elfload: Move PT_INTERP detection to first loop
For BTI, we need to know if the executable is static or dynamic,
which means looking for PT_INTERP earlier.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c7f17e7bd744dceff5708346d7c28ea2a08b7c18
https://github.com/qemu/qemu/commit/c7f17e7bd744dceff5708346d7c28ea2a08b7c18
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user/elfload: Use Error for load_elf_image
This is a bit clearer than open-coding some of this
with a bare c string.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-9-richard.henderson@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 808f656318109dfcb1c662002b0ebcb77d08c35a
https://github.com/qemu/qemu/commit/808f656318109dfcb1c662002b0ebcb77d08c35a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user/elfload: Use Error for load_elf_interp
This is slightly clearer than just using strerror, though
the different forms produced by error_setg_file_open and
error_setg_errno isn't entirely convenient.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-10-richard.henderson@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 83f990eb5adb898200b2290f3d89281ef60bc5c5
https://github.com/qemu/qemu/commit/83f990eb5adb898200b2290f3d89281ef60bc5c5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M linux-user/elfload.c
M linux-user/qemu.h
Log Message:
-----------
linux-user/elfload: Parse NT_GNU_PROPERTY_TYPE_0 notes
This is generic support, with the code disabled for all targets.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-11-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e8384b376e4c079cf05dfe158ed28455377b7cfd
https://github.com/qemu/qemu/commit/e8384b376e4c079cf05dfe158ed28455377b7cfd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user/elfload: Parse GNU_PROPERTY_AARCH64_FEATURE_1_AND
Use the new generic support for NT_GNU_PROPERTY_TYPE_0.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-12-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1d9ac91baf220367e68ca6a74955f2d60a4fc36b
https://github.com/qemu/qemu/commit/1d9ac91baf220367e68ca6a74955f2d60a4fc36b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/bti-1.c
A tests/tcg/aarch64/bti-2.c
A tests/tcg/aarch64/bti-crt.inc.c
M tests/tcg/configure.sh
Log Message:
-----------
tests/tcg/aarch64: Add bti smoke tests
The note test requires gcc 10 for -mbranch-protection=standard.
The mmap test uses PROT_BTI and does not require special compiler support.
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 83d5e19d3eedcf533d8be009a03c167b7e1ccf2e
https://github.com/qemu/qemu/commit/83d5e19d3eedcf533d8be009a03c167b7e1ccf2e
Author: Thomas Huth <thuth@redhat.com>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/highbank.c
Log Message:
-----------
hw/arm/highbank: Silence warnings about missing fallthrough statements
When compiling with -Werror=implicit-fallthrough, gcc complains about
missing fallthrough annotations in this file. Looking at the code,
the fallthrough is very likely intended here, so add some comments
to silence the compiler warnings.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-id: 20201020105938.23209-1-thuth@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7854104897444027759d805c133d9ea16c6a6c47
https://github.com/qemu/qemu/commit/7854104897444027759d805c133d9ea16c6a6c47
Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/xlnx-versal-virt.c
Log Message:
-----------
hw/arm: fix min_cpus for xlnx-versal-virt platform
This patch sets min_cpus field for xlnx-versal-virt platform,
because it always creates XLNX_VERSAL_NR_ACPUS cpus even with
-smp 1 command line option.
Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 160343854912.8460.17915238517799132371.stgit@pasha-ThinkPad-X280
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2ac88848cb03605e2fae6a035650eea461218af2
https://github.com/qemu/qemu/commit/2ac88848cb03605e2fae6a035650eea461218af2
Author: Havard Skinnemoen <hskinnemoen@google.com>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/timer/npcm7xx_timer.c
Log Message:
-----------
Move npcm7xx_timer_reached_zero call out of npcm7xx_timer_pause
This allows us to reuse npcm7xx_timer_pause for the watchdog timer.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7d378ed6e3b4a26f4da887fcccc4c6f1db3dcd42
https://github.com/qemu/qemu/commit/7d378ed6e3b4a26f4da887fcccc4c6f1db3dcd42
Author: Hao Wu <wuhaotsh@google.com>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M MAINTAINERS
M hw/arm/npcm7xx.c
M hw/misc/npcm7xx_clk.c
M hw/timer/npcm7xx_timer.c
M include/hw/misc/npcm7xx_clk.h
M include/hw/timer/npcm7xx_timer.h
M tests/qtest/meson.build
A tests/qtest/npcm7xx_watchdog_timer-test.c
Log Message:
-----------
hw/timer: Adding watchdog for NPCM7XX Timer.
The watchdog is part of NPCM7XX's timer module. Its behavior is
controlled by the WTCR register in the timer.
When enabled, the watchdog issues an interrupt signal after a pre-set
amount of cycles, and issues a reset signal shortly after that.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: deleted blank line at end of npcm_watchdog_timer-test.c]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 326ccfe240ca9ef4f659a241b39390fa956e999b
https://github.com/qemu/qemu/commit/326ccfe240ca9ef4f659a241b39390fa956e999b
Author: Havard Skinnemoen <hskinnemoen@google.com>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M docs/system/arm/nuvoton.rst
M hw/arm/npcm7xx.c
M hw/misc/meson.build
A hw/misc/npcm7xx_rng.c
M hw/misc/trace-events
M include/hw/arm/npcm7xx.h
A include/hw/misc/npcm7xx_rng.h
M tests/qtest/meson.build
A tests/qtest/npcm7xx_rng-test.c
Log Message:
-----------
hw/misc: Add npcm7xx random number generator
The RNG module returns a byte of randomness when the Data Valid bit is
set.
This implementation ignores the prescaler setting, and loads a new value
into RNGD every time RNGCS is read while the RNG is enabled and random
data is available.
A qtest featuring some simple randomness tests is included.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e23e7b12594ec0804c2d9f509f71841c82a62d1c
https://github.com/qemu/qemu/commit/e23e7b12594ec0804c2d9f509f71841c82a62d1c
Author: Havard Skinnemoen <hskinnemoen@google.com>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M docs/system/arm/nuvoton.rst
M hw/arm/npcm7xx.c
M hw/usb/hcd-ehci-sysbus.c
M hw/usb/hcd-ehci.h
M include/hw/arm/npcm7xx.h
Log Message:
-----------
hw/arm/npcm7xx: Add EHCI and OHCI controllers
The NPCM730 and NPCM750 chips have a single USB host port shared between
a USB 2.0 EHCI host controller and a USB 1.1 OHCI host controller. This
adds support for both of them.
Testing notes:
* With -device usb-kbd, qemu will automatically insert a full-speed
hub, and the keyboard becomes controlled by the OHCI controller.
* With -device usb-kbd,bus=usb-bus.0,port=1, the keyboard is directly
attached to the port without any hubs, and the device becomes
controlled by the EHCI controller since it's high speed capable.
* With -device usb-kbd,bus=usb-bus.0,port=1,usb_version=1, the
keyboard is directly attached to the port, but it only advertises
itself as full-speed capable, so it becomes controlled by the OHCI
controller.
In all cases, the keyboard device enumerates correctly.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 526dbbe087475599589ada4df70a337c09ae0f3f
https://github.com/qemu/qemu/commit/526dbbe087475599589ada4df70a337c09ae0f3f
Author: Havard Skinnemoen <hskinnemoen@google.com>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M docs/system/arm/nuvoton.rst
M hw/arm/npcm7xx.c
M hw/gpio/meson.build
A hw/gpio/npcm7xx_gpio.c
M hw/gpio/trace-events
M include/hw/arm/npcm7xx.h
A include/hw/gpio/npcm7xx_gpio.h
M tests/qtest/meson.build
A tests/qtest/npcm7xx_gpio-test.c
Log Message:
-----------
hw/gpio: Add GPIO model for Nuvoton NPCM7xx
The NPCM7xx chips have multiple GPIO controllers that are mostly
identical except for some minor differences like the reset values of
some registers. Each controller controls up to 32 pins.
Each individual pin is modeled as a pair of unnamed GPIOs -- one for
emitting the actual pin state, and one for driving the pin externally.
Like the nRF51 GPIO controller, a gpio level may be negative, which
means the pin is not driven, or floating.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a55aab618163f9ffd8b5cbf737d4e57875264510
https://github.com/qemu/qemu/commit/a55aab618163f9ffd8b5cbf737d4e57875264510
Author: Zenghui Yu <yuzenghui@huawei.com>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly
Ensure the vSMMUv3 will be restored before all PCIe devices so that DMA
translation can work properly during migration.
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Message-id: 20201019091508.197-1-yuzenghui@huawei.com
Acked-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 58b350280e9782bf564bf55cf872edb8143a49a8
https://github.com/qemu/qemu/commit/58b350280e9782bf564bf55cf872edb8143a49a8
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/bcm2836.c
M include/hw/arm/bcm2836.h
Log Message:
-----------
hw/arm/bcm2836: Restrict BCM283XInfo declaration to C source
No code out of bcm2836.c uses (or requires) the BCM283XInfo
declarations. Move it locally to the C source file.
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201024170127.3592182-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 34d1a4f591efd22ed7ff9c883f1328eca6b0741f
https://github.com/qemu/qemu/commit/34d1a4f591efd22ed7ff9c883f1328eca6b0741f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/bcm2836.c
Log Message:
-----------
hw/arm/bcm2836: QOM'ify more by adding class_init() to each SoC type
Remove usage of TypeInfo::class_data. Instead fill the fields in
the corresponding class_init().
So far all children use the same values for almost all fields,
but we are going to add the BCM2711/BCM2838 SoC for the raspi4
machine which use different fields.
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201024170127.3592182-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 25ea28845969c6f5b63b4b34c40c6cb743280b92
https://github.com/qemu/qemu/commit/25ea28845969c6f5b63b4b34c40c6cb743280b92
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/bcm2836.c
Log Message:
-----------
hw/arm/bcm2836: Introduce BCM283XClass::core_count
The BCM2835 has only one core. Introduce the core_count field to
be able to use values different than BCM283X_NCPUS (4).
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201024170127.3592182-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 96c741d7ce94741234e4ccad0d08c0055dd48c7e
https://github.com/qemu/qemu/commit/96c741d7ce94741234e4ccad0d08c0055dd48c7e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/bcm2836.c
Log Message:
-----------
hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs
It makes no sense to set enabled-cpus=0 on single core SoCs.
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201024170127.3592182-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f5600924ad42fba8eb5e30778baff6b4a5644070
https://github.com/qemu/qemu/commit/f5600924ad42fba8eb5e30778baff6b4a5644070
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/bcm2836.c
Log Message:
-----------
hw/arm/bcm2836: Split out common realize() code
The realize() function is clearly composed of two parts,
each described by a comment:
void realize()
{
/* common peripherals from bcm2835 */
...
/* bcm2836 interrupt controller (and mailboxes, etc.) */
...
}
Split the two part, so we can reuse the common part with other
SoCs from this family.
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201024170127.3592182-6-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: df6cf08dea890b691fafabd8a7ae8387ff2c8143
https://github.com/qemu/qemu/commit/df6cf08dea890b691fafabd8a7ae8387ff2c8143
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/bcm2836.c
M hw/arm/raspi.c
M include/hw/arm/bcm2836.h
Log Message:
-----------
hw/arm/bcm2836: Introduce the BCM2835 SoC
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201024170127.3592182-7-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ac6bc6ebb44d252b75398fbde887084dfd7bd31c
https://github.com/qemu/qemu/commit/ac6bc6ebb44d252b75398fbde887084dfd7bd31c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Add the Raspberry Pi A+ machine
The Pi A is almost the first machine released.
It uses a BCM2835 SoC which includes a ARMv6Z core.
Example booting the machine using content from [*]
(we use the device tree from the B model):
$ qemu-system-arm -M raspi1ap -serial stdio \
-kernel raspberrypi/firmware/boot/kernel.img \
-dtb raspberrypi/firmware/boot/bcm2708-rpi-b-plus.dtb \
-append 'earlycon=pl011,0x20201000 console=ttyAMA0'
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3
(crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST
2020
[ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7),
cr=00c5387d
[ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache
[ 0.000000] OF: fdt: Machine model: Raspberry Pi Model B+
...
[*]
http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201024170127.3592182-8-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3c8f9927fd435bb8d4865c0f261ed206e14e139a
https://github.com/qemu/qemu/commit/3c8f9927fd435bb8d4865c0f261ed206e14e139a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Add the Raspberry Pi Zero machine
Similarly to the Pi A, the Pi Zero uses a BCM2835 SoC (ARMv6Z core).
The only difference between the revision 1.2 and 1.3 is the latter
exposes a CSI camera connector. As we do not implement the Unicam
peripheral, there is no point in exposing a camera connector :)
Therefore we choose to model the 1.2 revision.
Example booting the machine using content from [*]:
$ qemu-system-arm -M raspi0 -serial stdio \
-kernel raspberrypi/firmware/boot/kernel.img \
-dtb raspberrypi/firmware/boot/bcm2708-rpi-zero.dtb \
-append 'printk.time=0 earlycon=pl011,0x20201000 console=ttyAMA0'
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3
(crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST
2020
[ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7),
cr=00c5387d
[ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache
[ 0.000000] OF: fdt: Machine model: Raspberry Pi Zero
...
[*]
http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201024170127.3592182-9-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5be94252d3497c29c0640e816903a148a4370153
https://github.com/qemu/qemu/commit/5be94252d3497c29c0640e816903a148a4370153
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Add the Raspberry Pi 3 model A+
The Pi 3A+ is a stripped down version of the 3B:
- 512 MiB of RAM instead of 1 GiB
- no on-board ethernet chipset
Add it as it is a closer match to what we model.
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201024170127.3592182-10-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 43f828e155b443641765a1e933100a96f26be3dd
https://github.com/qemu/qemu/commit/43f828e155b443641765a1e933100a96f26be3dd
Author: Dr. David Alan Gilbert <dgilbert@redhat.com>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/trace-events
Log Message:
-----------
arm/trace: Fix hex printing
Use of 0x%d - make up our mind as 0x%x
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20201014193355.53074-1-dgilbert@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f6f3c9b0f783d47ffab961ea18685e30a85f5818
https://github.com/qemu/qemu/commit/f6f3c9b0f783d47ffab961ea18685e30a85f5818
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M include/hw/clock.h
Log Message:
-----------
hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a6414d3b59fe8666a7b093cdcf23c747ce3055b8
https://github.com/qemu/qemu/commit/a6414d3b59fe8666a7b093cdcf23c747ce3055b8
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/core/clock.c
M hw/core/trace-events
Log Message:
-----------
hw/core/clock: trace clock values in Hz instead of ns
The nanosecond unit greatly limits the dynamic range we can display in
clock value traces, for values in the order of 1GHz and more. The
internal representation can go way beyond this value and it is quite
common for today's clocks to be within those ranges.
For example, a frequency between 500MHz+ and 1GHz will be displayed as
1ns. Beyond 1GHz, it will show up as 0ns.
Replace nanosecond periods traces with frequencies in the Hz unit
to have more dynamic range in the trace output.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 74de7145fd670bb8f86ceb2423c39c8dee37b820
https://github.com/qemu/qemu/commit/74de7145fd670bb8f86ceb2423c39c8dee37b820
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/bcm2835_peripherals.c
M include/hw/arm/bcm2835_peripherals.h
M include/hw/arm/raspi_platform.h
Log Message:
-----------
hw/arm/raspi: fix CPRMAN base address
The CPRMAN (clock controller) was mapped at the watchdog/power manager
address. It was also split into two unimplemented peripherals (CM and
A2W) but this is really the same one, as shown by this extract of the
Raspberry Pi 3 Linux device tree:
watchdog@7e100000 {
compatible = "brcm,bcm2835-pm\0brcm,bcm2835-pm-wdt";
[...]
reg = <0x7e100000 0x114 0x7e00a000 0x24>;
[...]
};
[...]
cprman@7e101000 {
compatible = "brcm,bcm2835-cprman";
[...]
reg = <0x7e101000 0x2000>;
[...]
};
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fc14176ba23de1386d8172d86a8006d9f8a555fc
https://github.com/qemu/qemu/commit/fc14176ba23de1386d8172d86a8006d9f8a555fc
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/bcm2835_peripherals.c
A hw/misc/bcm2835_cprman.c
M hw/misc/meson.build
M hw/misc/trace-events
M include/hw/arm/bcm2835_peripherals.h
A include/hw/misc/bcm2835_cprman.h
A include/hw/misc/bcm2835_cprman_internals.h
Log Message:
-----------
hw/arm/raspi: add a skeleton implementation of the CPRMAN
The BCM2835 CPRMAN is the clock manager of the SoC. It is composed of a
main oscillator, and several sub-components (PLLs, multiplexers, ...) to
generate the BCM2835 clock tree.
This commit adds a skeleton of the CPRMAN, with a dummy register
read/write implementation. It embeds the main oscillator (xosc) from
which all the clocks will be derived.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1e986e25d03c0d579843c4d3e2915b2f4ac8e47f
https://github.com/qemu/qemu/commit/1e986e25d03c0d579843c4d3e2915b2f4ac8e47f
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/misc/bcm2835_cprman.c
M include/hw/misc/bcm2835_cprman.h
M include/hw/misc/bcm2835_cprman_internals.h
Log Message:
-----------
hw/misc/bcm2835_cprman: add a PLL skeleton implementation
There are 5 PLLs in the CPRMAN, namely PLL A, C, D, H and B. All of them
take the xosc clock as input and produce a new clock.
This commit adds a skeleton implementation for the PLLs as sub-devices
of the CPRMAN. The PLLs are instantiated and connected internally to the
main oscillator.
Each PLL has 6 registers : CM, A2W_CTRL, A2W_ANA[0,1,2,3], A2W_FRAC. A
write to any of them triggers a call to the (not yet implemented)
pll_update function.
If the main oscillator changes frequency, an update is also triggered.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6d2b874cf1a6f595df805835325e9124c26f3dbf
https://github.com/qemu/qemu/commit/6d2b874cf1a6f595df805835325e9124c26f3dbf
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/misc/bcm2835_cprman.c
M include/hw/misc/bcm2835_cprman_internals.h
Log Message:
-----------
hw/misc/bcm2835_cprman: implement PLLs behaviour
The CPRMAN PLLs generate a clock based on a prescaler, a multiplier and
a divider. The prescaler doubles the parent (xosc) frequency, then the
multiplier/divider are applied. The multiplier has an integer and a
fractional part.
This commit also implements the CPRMAN CM_LOCK register. This register
reports which PLL is currently locked. We consider a PLL has being
locked as soon as it is enabled (on real hardware, there is a delay
after turning a PLL on, for it to stabilize).
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 09d56bbc9bc2f40865764b06b9830a9504bd3f9a
https://github.com/qemu/qemu/commit/09d56bbc9bc2f40865764b06b9830a9504bd3f9a
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/misc/bcm2835_cprman.c
M include/hw/misc/bcm2835_cprman.h
M include/hw/misc/bcm2835_cprman_internals.h
Log Message:
-----------
hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation
PLLs are composed of multiple channels. Each channel outputs one clock
signal. They are modeled as one device taking the PLL generated clock as
input, and outputting a new clock.
A channel shares the CM register with its parent PLL, and has its own
A2W_CTRL register. A write to the CM register will trigger an update of
the PLL and all its channels, while a write to an A2W_CTRL channel
register will update the required channel only.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 957458111280e7772cffc1ccbac75a5270e9267f
https://github.com/qemu/qemu/commit/957458111280e7772cffc1ccbac75a5270e9267f
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/misc/bcm2835_cprman.c
Log Message:
-----------
hw/misc/bcm2835_cprman: implement PLL channels behaviour
A PLL channel is able to further divide the generated PLL frequency.
The divider is given in the CTRL_A2W register. Some channels have an
additional fixed divider which is always applied to the signal.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7281362484ac1c1bc854ca17291c4078e870eec2
https://github.com/qemu/qemu/commit/7281362484ac1c1bc854ca17291c4078e870eec2
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/misc/bcm2835_cprman.c
M include/hw/misc/bcm2835_cprman.h
M include/hw/misc/bcm2835_cprman_internals.h
Log Message:
-----------
hw/misc/bcm2835_cprman: add a clock mux skeleton implementation
The clock multiplexers are the last clock stage in the CPRMAN. Each mux
outputs one clock signal that goes out of the CPRMAN to the SoC
peripherals.
Each mux has at most 10 sources. The sources 0 to 3 are common to all
muxes. They are:
0. ground (no clock signal)
1. the main oscillator (xosc)
2. "test debug 0" clock
3. "test debug 1" clock
Test debug 0 and 1 are actual clock muxes that can be used as sources to
other muxes (for debug purpose).
Sources 4 to 9 are mux specific and can be unpopulated (grounded). Those
sources are fed by the PLL channels outputs.
One corner case exists for DSI0E and DSI0P muxes. They have their source
number 4 connected to an intermediate multiplexer that can select
between PLLA-DSI0 and PLLD-DSI0 channel. This multiplexer is called
DSI0HSCK and is not a clock mux as such. It is really a simple mux from
the hardware point of view (see https://elinux.org/The_Undocumented_Pi).
This mux is not implemented in this commit.
Note that there is some muxes for which sources are unknown (because of
a lack of documentation). For those cases all the sources are connected
to ground in this implementation.
Each clock mux output is exported by the CPRMAN at the qdev level,
adding the suffix '-out' to the mux name to form the output clock name.
(E.g. the 'uart' mux sees its output exported as 'uart-out' at the
CPRMAN level.)
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fc9840850ba0eb3e61c81894bff3df12b0534497
https://github.com/qemu/qemu/commit/fc9840850ba0eb3e61c81894bff3df12b0534497
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/misc/bcm2835_cprman.c
Log Message:
-----------
hw/misc/bcm2835_cprman: implement clock mux behaviour
A clock mux can be configured to select one of its 10 sources through
the CM_CTL register. It also embeds yet another clock divider, composed
of an integer part and a fractional part. The number of bits of each
part is mux dependent.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 502960ca04c15cc7e24f3e8f9e0d8070bc3d77d7
https://github.com/qemu/qemu/commit/502960ca04c15cc7e24f3e8f9e0d8070bc3d77d7
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/misc/bcm2835_cprman.c
M include/hw/misc/bcm2835_cprman.h
M include/hw/misc/bcm2835_cprman_internals.h
Log Message:
-----------
hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer
This simple mux sits between the PLL channels and the DSI0E and DSI0P
clock muxes. This mux selects between PLLA-DSI0 and PLLD-DSI0 channel
and outputs the selected signal to source number 4 of DSI0E/P clock
muxes. It is controlled by the cm_dsi0hsck register.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 83ad469547812bb77faec1e98226f2859ab158d9
https://github.com/qemu/qemu/commit/83ad469547812bb77faec1e98226f2859ab158d9
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/misc/bcm2835_cprman.c
M include/hw/misc/bcm2835_cprman_internals.h
Log Message:
-----------
hw/misc/bcm2835_cprman: add sane reset values to the registers
Those reset values have been extracted from a Raspberry Pi 3 model B
v1.2, using the 2020-08-20 version of raspios. The dump was done using
the debugfs interface of the CPRMAN driver in Linux (under
'/sys/kernel/debug/clk'). Each exposed clock tree stage (PLLs, channels
and muxes) can be observed by reading the 'regdump' file (e.g.
'plla/regdump').
Those values are set by the Raspberry Pi firmware at boot time (Linux
expects them to be set when it boots up).
Some stages are not exposed by the Linux driver (e.g. the PLL B). For
those, the reset values are unknown and left to 0 which implies a
disabled output.
Once booted in QEMU, the final clock tree is very similar to the one
visible on real hardware. The differences come from some unimplemented
devices for which the driver simply disable the corresponding clock.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: aac63e0e6ea30b521370d3e3477cdcec17035d02
https://github.com/qemu/qemu/commit/aac63e0e6ea30b521370d3e3477cdcec17035d02
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/char/pl011.c
M hw/char/trace-events
M include/hw/char/pl011.h
Log Message:
-----------
hw/char/pl011: add a clock input
Add a clock input to the PL011 UART so we can compute the current baud
rate and trace it. This is intended for developers who wish to use QEMU
to e.g. debug their firmware or to figure out the baud rate configured
by an unknown/closed source binary.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 581bb849f749b6c51864989094399c77283b3d6c
https://github.com/qemu/qemu/commit/581bb849f749b6c51864989094399c77283b3d6c
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/bcm2835_peripherals.c
Log Message:
-----------
hw/arm/bcm2835_peripherals: connect the UART clock
Connect the 'uart-out' clock from the CPRMAN to the PL011 instance.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4204c5f70360dc1e527e65eb225d0688993fdcef
https://github.com/qemu/qemu/commit/4204c5f70360dc1e527e65eb225d0688993fdcef
Author: Shashi Mallela <shashi.mallela@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/Kconfig
M hw/watchdog/Kconfig
M hw/watchdog/meson.build
A hw/watchdog/sbsa_gwdt.c
A include/hw/watchdog/sbsa_gwdt.h
Log Message:
-----------
hw/watchdog: Implement SBSA watchdog device
Generic watchdog device model implementation as per ARM SBSA v6.0
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Message-id: 20201027015927.29495-2-shashi.mallela@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: baabe7d03c0bd57735cff998d2369c1a4f7cfb5c
https://github.com/qemu/qemu/commit/baabe7d03c0bd57735cff998d2369c1a4f7cfb5c
Author: Shashi Mallela <shashi.mallela@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/arm/sbsa-ref.c
Log Message:
-----------
hw/arm/sbsa-ref: add SBSA watchdog device
Included the newly implemented SBSA generic watchdog device model into
SBSA platform
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201027015927.29495-3-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 68d59c6d8d85ae176d3cb2cd20a48d6a090ba288
https://github.com/qemu/qemu/commit/68d59c6d8d85ae176d3cb2cd20a48d6a090ba288
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/core/ptimer.c
Log Message:
-----------
hw/core/ptimer: Support ptimer being disabled by timer callback
In ptimer_reload(), we call the callback function provided by the
timer device that is using the ptimer. This callback might disable
the ptimer. The code mostly handles this correctly, except that
we'll still print the warning about "Timer with delta zero,
disabling" if the now-disabled timer happened to be set such that it
would fire again immediately if it were enabled (eg because the
limit/reload value is zero).
Suppress the spurious warning message and the unnecessary
repeat-deletion of the underlying timer in this case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20201015151829.14656-2-peter.maydell@linaro.org
Commit: 32bd322a0134ed89db00f2b9b3894982db3dedcb
https://github.com/qemu/qemu/commit/32bd322a0134ed89db00f2b9b3894982db3dedcb
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-27 (Tue, 27 Oct 2020)
Changed paths:
M hw/timer/armv7m_systick.c
M include/hw/timer/armv7m_systick.h
Log Message:
-----------
hw/timer/armv7m_systick: Rewrite to use ptimers
The armv7m systick timer is a 24-bit decrementing, wrap-on-zero,
clear-on-write counter. Our current implementation has various
bugs and dubious workarounds in it (for instance see
https://bugs.launchpad.net/qemu/+bug/1872237).
We have an implementation of a simple decrementing counter
and we put a lot of effort into making sure it handles the
interesting corner cases (like "spend a cycle at 0 before
reloading") -- ptimer.
Rewrite the systick timer to use a ptimer rather than
a raw QEMU timer.
Unfortunately this is a migration compatibility break,
which will affect all M-profile boards.
Among other bugs, this fixes
https://bugs.launchpad.net/qemu/+bug/1872237 :
now writes to SYST_CVR when the timer is enabled correctly
do nothing; when the timer is enabled via SYST_CSR.ENABLE,
the ptimer code will (because of POLICY_NO_IMMEDIATE_RELOAD)
arrange that after one timer tick the counter is reloaded
from SYST_RVR and then counts down from there, as the
architecture requires.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201015151829.14656-3-peter.maydell@linaro.org
Commit: 802427bcdae1ad2eceea8a8877ecad835e3f8fde
https://github.com/qemu/qemu/commit/802427bcdae1ad2eceea8a8877ecad835e3f8fde
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-29 (Thu, 29 Oct 2020)
Changed paths:
M MAINTAINERS
M docs/system/arm/nuvoton.rst
M hw/arm/Kconfig
M hw/arm/bcm2835_peripherals.c
M hw/arm/bcm2836.c
M hw/arm/highbank.c
M hw/arm/npcm7xx.c
M hw/arm/raspi.c
M hw/arm/sbsa-ref.c
M hw/arm/smmuv3.c
M hw/arm/trace-events
M hw/arm/xlnx-versal-virt.c
M hw/char/pl011.c
M hw/char/trace-events
M hw/core/clock.c
M hw/core/ptimer.c
M hw/core/trace-events
M hw/gpio/meson.build
A hw/gpio/npcm7xx_gpio.c
M hw/gpio/trace-events
A hw/misc/bcm2835_cprman.c
M hw/misc/meson.build
M hw/misc/npcm7xx_clk.c
A hw/misc/npcm7xx_rng.c
M hw/misc/trace-events
M hw/timer/armv7m_systick.c
M hw/timer/npcm7xx_timer.c
M hw/usb/hcd-ehci-sysbus.c
M hw/usb/hcd-ehci.h
M hw/watchdog/Kconfig
M hw/watchdog/meson.build
A hw/watchdog/sbsa_gwdt.c
M include/elf.h
M include/exec/cpu-all.h
M include/hw/arm/bcm2835_peripherals.h
M include/hw/arm/bcm2836.h
M include/hw/arm/npcm7xx.h
M include/hw/arm/raspi_platform.h
M include/hw/char/pl011.h
M include/hw/clock.h
A include/hw/gpio/npcm7xx_gpio.h
A include/hw/misc/bcm2835_cprman.h
A include/hw/misc/bcm2835_cprman_internals.h
M include/hw/misc/npcm7xx_clk.h
A include/hw/misc/npcm7xx_rng.h
M include/hw/timer/armv7m_systick.h
M include/hw/timer/npcm7xx_timer.h
A include/hw/watchdog/sbsa_gwdt.h
M linux-user/aarch64/signal.c
M linux-user/elfload.c
M linux-user/mmap.c
M linux-user/qemu.h
M linux-user/syscall_defs.h
M target/arm/cpu.h
M target/arm/translate-a64.c
M tests/qtest/meson.build
A tests/qtest/npcm7xx_gpio-test.c
A tests/qtest/npcm7xx_rng-test.c
A tests/qtest/npcm7xx_watchdog_timer-test.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/bti-1.c
A tests/tcg/aarch64/bti-2.c
A tests/tcg/aarch64/bti-crt.inc.c
M tests/tcg/configure.sh
Log Message:
-----------
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20201027-1' into staging
target-arm queue:
* raspi: add model of cprman clock manager
* sbsa-ref: add an SBSA generic watchdog device
* arm/trace: Fix hex printing
* raspi: Add models of Pi 3 model A+, Pi Zero and Pi A+
* hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly
* Nuvoton NPCM7xx: Add USB, RNG, GPIO and watchdog support
* hw/arm: fix min_cpus for xlnx-versal-virt platform
* hw/arm/highbank: Silence warnings about missing fallthrough statements
* linux-user: Support Aarch64 BTI
* Armv7M systick: fix corner case bugs by rewriting to use ptimer
# gpg: Signature made Tue 27 Oct 2020 11:27:10 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20201027-1: (48 commits)
hw/timer/armv7m_systick: Rewrite to use ptimers
hw/core/ptimer: Support ptimer being disabled by timer callback
hw/arm/sbsa-ref: add SBSA watchdog device
hw/watchdog: Implement SBSA watchdog device
hw/arm/bcm2835_peripherals: connect the UART clock
hw/char/pl011: add a clock input
hw/misc/bcm2835_cprman: add sane reset values to the registers
hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer
hw/misc/bcm2835_cprman: implement clock mux behaviour
hw/misc/bcm2835_cprman: add a clock mux skeleton implementation
hw/misc/bcm2835_cprman: implement PLL channels behaviour
hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation
hw/misc/bcm2835_cprman: implement PLLs behaviour
hw/misc/bcm2835_cprman: add a PLL skeleton implementation
hw/arm/raspi: add a skeleton implementation of the CPRMAN
hw/arm/raspi: fix CPRMAN base address
hw/core/clock: trace clock values in Hz instead of ns
hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro
arm/trace: Fix hex printing
hw/arm/raspi: Add the Raspberry Pi 3 model A+
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/c0444009147a...802427bcdae1
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