[Qemu-commits] [qemu/qemu] 4565d8: hw/arm: versal: Use nr_apu_cpus in favor of hard c...

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 4565d826163d2e3a4ca3a5ebf3904e6b3b04a487
      
https://github.com/qemu/qemu/commit/4565d826163d2e3a4ca3a5ebf3904e6b3b04a487
  Author: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
  Date:   2021-02-11 (Thu, 11 Feb 2021)

  Changed paths:
    M hw/arm/xlnx-versal.c

  Log Message:
  -----------
  hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2

Use nr_apu_cpus in favor of hard coding 2.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210210142048.3125878-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621
      
https://github.com/qemu/qemu/commit/d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621
  Author: Daniel Müller <muellerd@fb.com>
  Date:   2021-02-11 (Thu, 11 Feb 2021)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Correctly initialize MDCR_EL2.HPMN

When working with performance monitoring counters, we look at
MDCR_EL2.HPMN as part of the check whether a counter is enabled. This
check fails, because MDCR_EL2.HPMN is reset to 0, meaning that no
counters are "enabled" for < EL2.
That's in violation of the Arm specification, which states that

> On a Warm reset, this field [MDCR_EL2.HPMN] resets to the value in
> PMCR_EL0.N

That's also what a comment in the code acknowledges, but the necessary
adjustment seems to have been forgotten when support for more counters
was added.
This change fixes the issue by setting the reset value to PMCR.N, which
is four.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: eac92d316351b855ba79eb374dd21cc367f1f9c1
      
https://github.com/qemu/qemu/commit/eac92d316351b855ba79eb374dd21cc367f1f9c1
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-02-11 (Thu, 11 Feb 2021)

  Changed paths:
    M accel/tcg/cpu-exec.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/musca.c
    M hw/arm/npcm7xx.c
    M hw/arm/xlnx-versal.c
    M hw/misc/arm_integrator_debug.c
    M hw/timer/arm_timer.c
    M include/hw/dma/pl080.h
    M include/hw/misc/arm_integrator_debug.h
    M include/hw/ssi/pl022.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper-a64.c
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/machine.c
    M target/arm/op_helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20210211-1' into staging

target-arm queue:
 * Correctly initialize MDCR_EL2.HPMN
 * versal: Use nr_apu_cpus in favor of hard coding 2
 * accel/tcg: Add URL of clang bug to comment about our workaround
 * Add support for FEAT_DIT, Data Independent Timing
 * Remove GPIO from unimplemented NPCM7XX
 * Fix SCR RES1 handling
 * Don't migrate CPUARMState.features

# gpg: Signature made Thu 11 Feb 2021 19:56:40 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210211-1:
  target/arm: Correctly initialize MDCR_EL2.HPMN
  hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
  accel/tcg: Add URL of clang bug to comment about our workaround
  arm: Update infocenter.arm.com URLs
  target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
  target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
  target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
  target/arm: Add support for FEAT_DIT, Data Independent Timing
  hw/arm: Remove GPIO from unimplemented NPCM7XX
  target/arm: Fix SCR RES1 handling
  target/arm: Don't migrate CPUARMState.features

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/54ebfee79cc9...eac92d316351