[Qemu-commits] [qemu/qemu] 5f1fff: docs: fix link in sbsa description

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[Qemu-commits] [qemu/qemu] 5f1fff: docs: fix link in sbsa description

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 5f1fff: docs: fix link in sbsa description
Date:	Mon, 10 May 2021 07:37:03 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 5f1fffa0a6575cfb39834d36c52e973a95dfb275
      
https://github.com/qemu/qemu/commit/5f1fffa0a6575cfb39834d36c52e973a95dfb275
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M docs/system/arm/sbsa.rst

  Log Message:
  -----------
  docs: fix link in sbsa description

A trailing _ makes all the difference to the rendered link.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210428131316.31390-1-alex.bennee@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 68948d18224b93361e2880e2946ab268d0c650d7
      
https://github.com/qemu/qemu/commit/68948d18224b93361e2880e2946ab268d0c650d7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user/aarch64: Enable hwcap for RND, BTI, and MTE

These three features are already enabled by TCG, but are missing
their hwcap bits.  Update HWCAP2 from linux v5.12.

Cc: qemu-stable@nongnu.org (for 6.0.1)
Buglink: https://bugs.launchpad.net/bugs/1926044
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210427214108.88503-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: eb849d8fd542329b299be5a894d7e272eed16a49
      
https://github.com/qemu/qemu/commit/eb849d8fd542329b299be5a894d7e272eed16a49
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write()

In tlbi_aa64_vae2is_write() the calculation
  bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2,
                            pageaddr)

has the two arms of the ?: expression reversed. Fix the bug.

Fixes: b6ad6062f1e5
Reported-by: Rebecca Cran <rebecca@nuviainc.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Rebecca Cran <rebecca@nuviainc.com>
Message-id: 20210420123106.10861-1-peter.maydell@linaro.org


  Commit: b5aa664679510645fa01f55590db60ca2657f7fc
      
https://github.com/qemu/qemu/commit/b5aa664679510645fa01f55590db60ca2657f7fc
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Move constant expanders to translate.h

Some of the constant expanders defined in translate.c are generically
useful and will be used by the separate C files for VFP and Neon once
they are created; move the expander definitions to translate.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-2-peter.maydell@linaro.org


  Commit: d9318a5f9c32225a9d5365758ae5a329b55de2fe
      
https://github.com/qemu/qemu/commit/d9318a5f9c32225a9d5365758ae5a329b55de2fe
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Share unallocated_encoding() and gen_exception_insn()

The unallocated_encoding() function is the same in both
translate-a64.c and translate.c; make the translate.c function global
and drop the translate-a64.c version.  To do this we need to also
share gen_exception_insn(), which currently exists in two slightly
different versions for A32 and A64: merge those into a single
function that can work for both.

This will be useful for splitting up translate.c, which will require
unallocated_encoding() to no longer be file-local.  It's also
hopefully less confusing to have only one version of the function
rather than two.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-3-peter.maydell@linaro.org


  Commit: 5ce389f2e76e8aa318ec734cc12c0f0e657a9e0e
      
https://github.com/qemu/qemu/commit/5ce389f2e76e8aa318ec734cc12c0f0e657a9e0e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    A target/arm/translate-a32.h
    M target/arm/translate-vfp.c.inc
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Make functions used by m-nocp global

We want to split out the .c.inc files which are currently included
into translate.c so they are separate compilation units.  To do this
we need to make some functions which are currently file-local to
translate.c have global scope; create a translate-a32.h paralleling
the existing translate-a64.h as a place for these declarations to
live, so that code moved into the new compilation units can call
them.

The functions made global here are those required by the
m-nocp.decode functions, except that I have converted the whole
family of {read,write}_neon_element* and also both the load_cpu and
store_cpu functions for consistency, even though m-nocp only wants a
few functions from each.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-4-peter.maydell@linaro.org


  Commit: 9a5071abbce614c52d0e72bdbd688cd4e2a9ee46
      
https://github.com/qemu/qemu/commit/9a5071abbce614c52d0e72bdbd688cd4e2a9ee46
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/meson.build
    M target/arm/translate-a32.h
    A target/arm/translate-m-nocp.c
    M target/arm/translate-vfp.c.inc
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Split m-nocp trans functions into their own file

Currently the trans functions for m-nocp.decode all live in
translate-vfp.inc.c; move them out into their own translation unit,
translate-m-nocp.c.

The trans_* functions here are pure code motion with no changes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-5-peter.maydell@linaro.org


  Commit: 73d2f5d2bbbfbe1be6930ae388f92946e913dcc9
      
https://github.com/qemu/qemu/commit/73d2f5d2bbbfbe1be6930ae388f92946e913dcc9
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/translate-a32.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Move gen_aa32 functions to translate-a32.h

Move the various gen_aa32* functions and macros out of translate.c
and into translate-a32.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-6-peter.maydell@linaro.org


  Commit: 06085d6a10e11fb9df871648668b072905936566
      
https://github.com/qemu/qemu/commit/06085d6a10e11fb9df871648668b072905936566
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/translate-vfp.c.inc
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc

The functions vfp_load_reg32(), vfp_load_reg64(), vfp_store_reg32()
and vfp_store_reg64() are used only in translate-vfp.c.inc. Move
them to that file.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-7-peter.maydell@linaro.org


  Commit: 4a800a739d6c7760a35b4be6a01bb3819de51030
      
https://github.com/qemu/qemu/commit/4a800a739d6c7760a35b4be6a01bb3819de51030
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/translate-a32.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Make functions used by translate-vfp global

Make the remaining functions which are needed by translate-vfp.c.inc
global.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-8-peter.maydell@linaro.org


  Commit: 45fbd5a96733c61a7bf85a382809bd9839afde94
      
https://github.com/qemu/qemu/commit/45fbd5a96733c61a7bf85a382809bd9839afde94
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/meson.build
    M target/arm/translate-a32.h
    A target/arm/translate-vfp.c
    R target/arm/translate-vfp.c.inc
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Make translate-vfp.c.inc its own compilation unit

Switch translate-vfp.c.inc from being #included into translate.c
to being its own compilation unit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-9-peter.maydell@linaro.org


  Commit: eb554d612d6a7718154babfc9e2b36694397b443
      
https://github.com/qemu/qemu/commit/eb554d612d6a7718154babfc9e2b36694397b443
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/translate-neon.c.inc
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Move vfp_reg_ptr() to translate-neon.c.inc

The function vfp_reg_ptr() is used only in translate-neon.c.inc;
move it there.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-10-peter.maydell@linaro.org


  Commit: 8e30454fed1e45d709942836f2e299c8d9b00837
      
https://github.com/qemu/qemu/commit/8e30454fed1e45d709942836f2e299c8d9b00837
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Delete unused typedef

The VFPGenFixPointFn typedef is unused; delete it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210430132740.10391-11-peter.maydell@linaro.org


  Commit: 9194a9cbc75e7af63eff26c87b995bdc52078ca6
      
https://github.com/qemu/qemu/commit/9194a9cbc75e7af63eff26c87b995bdc52078ca6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h

Move the NeonGenThreeOpEnvFn typedef to translate.h together
with the other similar typedefs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210430132740.10391-12-peter.maydell@linaro.org


  Commit: b5c8a457fab78e08d0ab5f9ca242b85b31c72c87
      
https://github.com/qemu/qemu/commit/b5c8a457fab78e08d0ab5f9ca242b85b31c72c87
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/translate-a32.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Make functions used by translate-neon global

Make the remaining functions needed by the translate-neon code
global.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-13-peter.maydell@linaro.org


  Commit: 4800b852b8099187d2186c213626c298a60b775c
      
https://github.com/qemu/qemu/commit/4800b852b8099187d2186c213626c298a60b775c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/meson.build
    M target/arm/translate-a32.h
    A target/arm/translate-neon.c
    R target/arm/translate-neon.c.inc
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Make translate-neon.c.inc its own compilation unit

Switch translate-neon.c.inc from being #included into translate.c
to being its own compilation unit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-14-peter.maydell@linaro.org


  Commit: 805a0a16c4d58c5d5bcdea7588d7060d3caa6c14
      
https://github.com/qemu/qemu/commit/805a0a16c4d58c5d5bcdea7588d7060d3caa6c14
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: Make WFI a NOP for userspace emulators

The WFI insn is not system-mode only, though it doesn't usually make
a huge amount of sense for userspace code to execute it.  Currently
if you try it in qemu-arm then the helper function will raise an
EXCP_HLT exception, which is not covered by the switch in cpu_loop()
and results in an abort:

qemu: unhandled CPU exception 0x10001 - aborting
R00=00000001 R01=408003e4 R02=408003ec R03=000102ec
R04=00010a28 R05=00010158 R06=00087460 R07=00010158
R08=00000000 R09=00000000 R10=00085b7c R11=408002a4
R12=408002b8 R13=408002a0 R14=0001057c R15=000102f8
PSR=60000010 -ZC- A usr32
qemu:handle_cpu_signal received signal outside vCPU context @ pc=0x7fcbfa4f0a12

Make the WFI helper function return immediately in the usermode
emulator. This turns WFI into a NOP, which is OK because:
 * architecturally "WFI is a NOP" is a permitted implementation
 * aarch64 Linux kernels use the SCTLR_EL1.nTWI bit to trap
   userspace WFI and NOP it (though aarch32 kernels currently
   just let WFI do whatever it would do)

We could in theory make the translate.c code special case user-mode
emulation and NOP the insn entirely rather than making the helper
do nothing, but because no real world code will be trying to
execute WFI we don't care about efficiency and the helper provides
a single place where we can make the change rather than having
to touch multiple places in translate.c and translate-a64.c.

Fixes: https://bugs.launchpad.net/qemu/+bug/1926759
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430162212.825-1-peter.maydell@linaro.org


  Commit: 4d4fbbe4a8faeac938f2cd5fa3ac1644d4838c71
      
https://github.com/qemu/qemu/commit/4d4fbbe4a8faeac938f2cd5fa3ac1644d4838c71
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M hw/sd/omap_mmc.c

  Log Message:
  -----------
  hw/sd/omap_mmc: Use device_cold_reset() instead of device_legacy_reset()

The omap_mmc_reset() function resets its SD card via
device_legacy_reset().  We know that the SD card does not have a qbus
of its own, so the new device_cold_reset() function (which resets
both the device and its child buses) is equivalent here to
device_legacy_reset() and we can just switch to the new API.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210430222348.8514-1-peter.maydell@linaro.org


  Commit: 5d251a4ae9dff6f7b496b9f57532c8251bd2866b
      
https://github.com/qemu/qemu/commit/5d251a4ae9dff6f7b496b9f57532c8251bd2866b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M include/qemu/osdep.h
    M include/sysemu/os-posix.h
    M include/sysemu/os-win32.h

  Log Message:
  -----------
  osdep: Make os-win32.h and os-posix.h handle 'extern "C"' themselves

Both os-win32.h and os-posix.h include system header files. Instead
of having osdep.h include them inside its 'extern "C"' block, make
these headers handle that themselves, so that we don't include the
system headers inside 'extern "C"'.

This doesn't fix any current problems, but it's conceptually the
right way to handle system headers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a5593cd60047f4d933e51d4723cfc6964194cd80
      
https://github.com/qemu/qemu/commit/a5593cd60047f4d933e51d4723cfc6964194cd80
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M include/qemu/bswap.h

  Log Message:
  -----------
  include/qemu/bswap.h: Handle being included outside extern "C" block

Make bswap.h handle being included outside an 'extern "C"' block:
all system headers are included first, then all declarations are
put inside an 'extern "C"' block.

This requires a little rearrangement as currently we have an ifdef
ladder that has some system includes and some local declarations
or definitions, and we need to separate those out.

We want to do this because dis-asm.h includes bswap.h, dis-asm.h
may need to be included from C++ files, and system headers should
not be included within 'extern "C"' blocks.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ae45ea1391dcacc3909f939570caaaa8f5f945b3
      
https://github.com/qemu/qemu/commit/ae45ea1391dcacc3909f939570caaaa8f5f945b3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M disas/arm-a64.cc
    M disas/nanomips.cpp
    M include/disas/dis-asm.h

  Log Message:
  -----------
  include/disas/dis-asm.h: Handle being included outside 'extern "C"'

Make dis-asm.h handle being included outside an 'extern "C"' block;
this allows us to remove the 'extern "C"' blocks that our two C++
files that include it are using.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ce0a67d45591c4e24815b8e7ae99686a2a80190c
      
https://github.com/qemu/qemu/commit/ce0a67d45591c4e24815b8e7ae99686a2a80190c
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M hw/arm/imx25_pdk.c

  Log Message:
  -----------
  hw/arm/imx25_pdk: Fix error message for invalid RAM size

The i.MX25 PDK board has 2 banks for SDRAM, each can
address up to 256 MiB. So the total RAM usable for this
board is 512M. When we ask for more we get a misleading
error message:

  $ qemu-system-arm -M imx25-pdk -m 513M
  qemu-system-arm: Invalid RAM size, should be 128 MiB

Update the error message to better match the reality:

  $ qemu-system-arm -M imx25-pdk -m 513M
  qemu-system-arm: RAM size more than 512 MiB is not supported

Fixes: bf350daae02 ("arm/imx25_pdk: drop RAM size fixup")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20210407225608.1882855-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9c278315ab392880baa14380f785c1086bd86ab2
      
https://github.com/qemu/qemu/commit/9c278315ab392880baa14380f785c1086bd86ab2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M include/hw/misc/mps2-scc.h

  Log Message:
  -----------
  hw/misc/mps2-scc: Add "QEMU interface" comment

The MPS2 SCC device doesn't have any documentation of its properties;
add a "QEMU interface" format comment describing them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210504120912.23094-2-peter.maydell@linaro.org


  Commit: d9a4f8c333869b04e0e0b13b18237496fa0b20b0
      
https://github.com/qemu/qemu/commit/d9a4f8c333869b04e0e0b13b18237496fa0b20b0
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M hw/misc/mps2-scc.c
    M include/hw/misc/mps2-scc.h

  Log Message:
  -----------
  hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping

On some boards, SCC config register CFG0 bit 0 controls whether
parts of the board memory map are remapped. Support this with:
 * a device property scc-cfg0 so the board can specify the
   initial value of the CFG0 register
 * an outbound GPIO line which tracks bit 0 and which the board
   can wire up to provide the remapping

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210504120912.23094-3-peter.maydell@linaro.org


  Commit: 51853b8245cbd0423eaeb09a6f6c09d3306071b9
      
https://github.com/qemu/qemu/commit/51853b8245cbd0423eaeb09a6f6c09d3306071b9
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M docs/system/arm/mps2.rst
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Implement AN524 memory remapping via machine property

The AN524 FPGA image supports two memory maps, which differ in where
the QSPI and BRAM are.  In the default map, the BRAM is at
0x0000_0000, and the QSPI at 0x2800_0000.  In the second map, they
are the other way around.

In hardware, the initial mapping can be selected by the user by
writing either "REMAP: BRAM" (the default) or "REMAP: QSPI" in the
board configuration file.  The board config file is acted on by the
"Motherboard Configuration Controller", which is an entirely separate
microcontroller on the dev board but outside the FPGA.

The guest can also dynamically change the mapping via the SCC
CFG_REG0 register.

Implement this functionality for QEMU, using a machine property
"remap" with valid values "BRAM" and "QSPI" to allow the user to set
the initial mapping, in the same way they can on the FPGA, and
wiring up the bit from the SCC register to also switch the mapping.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210504120912.23094-4-peter.maydell@linaro.org


  Commit: 8f96812baa53005f32aece3e30b140826c20aa19
      
https://github.com/qemu/qemu/commit/8f96812baa53005f32aece3e30b140826c20aa19
  Author: Guenter Roeck <linux@roeck-us.net>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M hw/arm/xilinx_zynq.c

  Log Message:
  -----------
  hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9

Commit dfc388797cc4 ("hw/arm: xlnx: Set all boards' GEM 'phy-addr'
property value to 23") configured the PHY address for xilinx-zynq-a9
to 23. When trying to boot xilinx-zynq-a9 with zynq-zc702.dtb or
zynq-zc706.dtb, this results in the following error message when
trying to use the Ethernet interface.

macb e000b000.ethernet eth0: Could not attach PHY (-19)

The devicetree files for ZC702 and ZC706 configure PHY address 7. The
documentation for the ZC702 and ZC706 evaluation boards suggest that the
PHY address is 7, not 23. Other boards use PHY address 0, 1, 3, or 7.
I was unable to find a documentation or a devicetree file suggesting
or using PHY address 23. The Ethernet interface starts working with
zynq-zc702.dtb and zynq-zc706.dtb when setting the PHY address to 7,
so let's use it.

Cc: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210504124140.1100346-1-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7b15b93a3db854e007bffdf375fb49e3c8ba193c
      
https://github.com/qemu/qemu/commit/7b15b93a3db854e007bffdf375fb49e3c8ba193c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M disas/arm-a64.cc
    M disas/nanomips.cpp
    M docs/system/arm/mps2.rst
    M docs/system/arm/sbsa.rst
    M hw/arm/imx25_pdk.c
    M hw/arm/mps2-tz.c
    M hw/arm/xilinx_zynq.c
    M hw/misc/mps2-scc.c
    M hw/sd/omap_mmc.c
    M include/disas/dis-asm.h
    M include/hw/misc/mps2-scc.h
    M include/qemu/bswap.h
    M include/qemu/osdep.h
    M include/sysemu/os-posix.h
    M include/sysemu/os-win32.h
    M linux-user/elfload.c
    M target/arm/helper.c
    M target/arm/meson.build
    M target/arm/op_helper.c
    A target/arm/translate-a32.h
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    A target/arm/translate-m-nocp.c
    A target/arm/translate-neon.c
    R target/arm/translate-neon.c.inc
    A target/arm/translate-vfp.c
    R target/arm/translate-vfp.c.inc
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210510' 
into staging

target-arm queue:
 * docs: fix link in sbsa description
 * linux-user/aarch64: Enable hwcap for RND, BTI, and MTE
 * target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write()
 * target/arm: Split neon and vfp translation to their own
   compilation units
 * target/arm: Make WFI a NOP for userspace emulators
 * hw/sd/omap_mmc: Use device_cold_reset() instead of
   device_legacy_reset()
 * include: More fixes for 'extern "C"' block use
 * hw/arm/imx25_pdk: Fix error message for invalid RAM size
 * hw/arm/mps2-tz: Implement AN524 memory remapping via machine property
 * hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9

# gpg: Signature made Mon 10 May 2021 13:25:06 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210510: (26 commits)
  hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9
  hw/arm/mps2-tz: Implement AN524 memory remapping via machine property
  hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping
  hw/misc/mps2-scc: Add "QEMU interface" comment
  hw/arm/imx25_pdk: Fix error message for invalid RAM size
  include/disas/dis-asm.h: Handle being included outside 'extern "C"'
  include/qemu/bswap.h: Handle being included outside extern "C" block
  osdep: Make os-win32.h and os-posix.h handle 'extern "C"' themselves
  hw/sd/omap_mmc: Use device_cold_reset() instead of device_legacy_reset()
  target/arm: Make WFI a NOP for userspace emulators
  target/arm: Make translate-neon.c.inc its own compilation unit
  target/arm: Make functions used by translate-neon global
  target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h
  target/arm: Delete unused typedef
  target/arm: Move vfp_reg_ptr() to translate-neon.c.inc
  target/arm: Make translate-vfp.c.inc its own compilation unit
  target/arm: Make functions used by translate-vfp global
  target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc
  target/arm: Move gen_aa32 functions to translate-a32.h
  target/arm: Split m-nocp trans functions into their own file
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/74e31681ba05...7b15b93a3db8
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