[Qemu-commits] [qemu/qemu] c6223d: target/riscv: Fix PMP propagation for

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[Qemu-commits] [qemu/qemu] c6223d: target/riscv: Fix PMP propagation for

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] c6223d: target/riscv: Fix PMP propagation for tlb
Date:	Tue, 03 Jan 2023 09:26:30 -0800
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: c6223d70d4e27fb26a845c07730c40117e8cfd03
      
https://github.com/qemu/qemu/commit/c6223d70d4e27fb26a845c07730c40117e8cfd03
  Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/cpu_helper.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h

  Log Message:
  -----------
  target/riscv: Fix PMP propagation for tlb

Only the pmp index that be checked by pmp_hart_has_privs can be used
by pmp_get_tlb_size to avoid an error pmp index.

Before modification, we may use an error pmp index. For example,
we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs. If there
is an pmp rule, valid range is [0x4fc, 0x500), then pmp_hart_has_privs
will return true;

However, this checked pmp index is discarded as pmp_hart_has_privs
return bool value. In pmp_is_range_in_tlb, it will traverse all pmp
rules. The tlb_sa will be 0x0, and tlb_ea will be 0xfff. If there is
a pmp rule [0x10, 0x14), it will be misused as it is legal in
pmp_get_tlb_size.

As we have already known the correct pmp index, just remove the
remove the pmp_is_range_in_tlb and get tlb size directly from
pmp_get_tlb_size.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221012060016.30856-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b2fe5201b520fb4c6871c90d4fd7830f91a331ba
      
https://github.com/qemu/qemu/commit/b2fe5201b520fb4c6871c90d4fd7830f91a331ba
  Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M include/hw/registerfields.h

  Log Message:
  -----------
  hw/registerfields: add `FIELDx_1CLEAR()` macro

Adds a helper macro that implements the register `w1c`
functionality.

Ex:
  uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);

If ANY bits of the specified `FIELD` is set
then the respective field is cleared and returned to `data`.

If the field is cleared (0), then no change and
val is returned.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221017054950.317584-2-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e4840b6f40bdb100a1859d15adb980a09b541c0c
      
https://github.com/qemu/qemu/commit/e4840b6f40bdb100a1859d15adb980a09b541c0c
  Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/ssi/ibex_spi_host.c

  Log Message:
  -----------
  hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro

use the `FIELD32_1CLEAR` macro to implement register
`rw1c` functionality to `ibex_spi`.

This change was tested by running the `SPI_HOST` from TockOS.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221017054950.317584-3-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bdba73933a711639edd278677a95c8be62cc1baf
      
https://github.com/qemu/qemu/commit/bdba73933a711639edd278677a95c8be62cc1baf
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Fix range matched by TCG_CT_CONST_M12

We were matching a signed 13-bit range, not a 12-bit range.
Expand the commentary within the function and be explicit
about all of the ranges.

Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221022095821.2441874-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cfa21ce0ad482019a50bc6c07a77c14721ec7391
      
https://github.com/qemu/qemu/commit/cfa21ce0ad482019a50bc6c07a77c14721ec7391
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Fix reg overlap case in tcg_out_addsub2

There was a typo using opc_addi instead of opc_add with the
two registers.  While we're at it, simplify the gating test
to al == bl to improve dynamic scheduling even when the
output register does not overlap the inputs.

Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221020233836.2341671-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: afb84b2784a16d7b0363e141e4787b4c01ed6a98
      
https://github.com/qemu/qemu/commit/afb84b2784a16d7b0363e141e4787b4c01ed6a98
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Fix base register for user-only qemu_ld/st

When guest_base != 0, we were not coordinating the usage of
TCG_REG_TMP0 as base properly, leading to a previous zero-extend
of the input address being discarded.

Shuffle the alignment check to the front, because that does not
depend on the zero-extend, and it keeps the register usage clear.
Set base after each step of the address arithmetic instead of before.

Return the base register used from tcg_out_tlb_load, so as to
keep that register choice localized to that function.

Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221023233337.2846860-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cb326f2565bd9dd58a83e0a0bb5a2009b52c06f7
      
https://github.com/qemu/qemu/commit/cb326f2565bd9dd58a83e0a0bb5a2009b52c06f7
  Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  hw/riscv/opentitan: bump opentitan

This patch updates the OpenTitan model to match
the specified register layout as per [1]. Which is also the latest
commit of OpenTitan supported by TockOS.

Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes
any references to Padctrl. Note: OpenTitan doc [2] has not yet specified
much detail regarding this, except for a note that states `TODO: this
section needs to be updated to reflect the pinmux/padctrl merger`

[1] 
https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
[2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/
[3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20221025043335.339815-2-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 16fa1caae89895b2da96a5251c88fbd4d3cdb1bd
      
https://github.com/qemu/qemu/commit/16fa1caae89895b2da96a5251c88fbd4d3cdb1bd
  Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  hw/riscv/opentitan: add aon_timer base unimpl

Adds the updated `aon_timer` base as an unimplemented device. This is
used by TockOS, patch ensures the guest doesn't hit load faults.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221025043335.339815-3-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 52022709aba69c1385fe99cdbe823166f73d394f
      
https://github.com/qemu/qemu/commit/52022709aba69c1385fe99cdbe823166f73d394f
  Author: Mayuresh Chitale <mchitale@ventanamicro.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: Add smstateen support

Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.

This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221016124726.102129-2-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b9283cc8d0e395763985af7e2d82e742ea01ebcb
      
https://github.com/qemu/qemu/commit/b9283cc8d0e395763985af7e2d82e742ea01ebcb
  Author: Mayuresh Chitale <mchitale@ventanamicro.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: smstateen check for h/s/envcfg

Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding
bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is
generated.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221016124726.102129-3-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e35e78de3cec59140f1c885c84de0f8ebf110fe2
      
https://github.com/qemu/qemu/commit/e35e78de3cec59140f1c885c84de0f8ebf110fe2
  Author: Mayuresh Chitale <mchitale@ventanamicro.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: generate virtual instruction exception

This patch adds a mechanism to generate a virtual instruction
instruction exception instead of an illegal instruction exception
during instruction decode when virt is enabled.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221016124726.102129-4-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: fe99a95e259abcfd8b7d1a3d5dc779606fa1ff4f
      
https://github.com/qemu/qemu/commit/fe99a95e259abcfd8b7d1a3d5dc779606fa1ff4f
  Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/debug.c
    M target/riscv/debug.h
    M target/riscv/helper.h
    M target/riscv/insn_trans/trans_privileged.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Add itrigger support when icount is not enabled

When icount is not enabled, there is no API in QEMU that can get the
guest instruction number.

Translate the guest code in a way that each TB only has one instruction.
After executing the instruction, decrease the count by 1 until it reaches 0
where the itrigger fires.

Note that only when priviledge matches the itrigger configuration,
the count will decrease.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-2-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 131ecf30772c29695b91ae561582be2fab70dd43
      
https://github.com/qemu/qemu/commit/131ecf30772c29695b91ae561582be2fab70dd43
  Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/debug.c
    M target/riscv/debug.h

  Log Message:
  -----------
  target/riscv: Add itrigger support when icount is enabled

The max count in itrigger can be 0x3FFF, which will cause a no trivial
translation and execution overload.

When icount is enabled, QEMU provides API that can fetch guest
instruction number. Thus, we can set an timer for itrigger with
the count as deadline.

Only when timer expires or priviledge mode changes, do lazy update
to count.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-3-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e789781ee2c0fe3b4cca42cffe60c6c1dc554d35
      
https://github.com/qemu/qemu/commit/e789781ee2c0fe3b4cca42cffe60c6c1dc554d35
  Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/debug.c

  Log Message:
  -----------
  target/riscv: Enable native debug itrigger

When QEMU is not in icount mode, execute instruction one by one. The
tdata1 can be read directly.

When QEMU is in icount mode, use a timer to simulate the itrigger. The
tdata1 may be not right because of lazy update of count in tdata1. Thus,
We should pack the adjusted count into tdata1 before read it back.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-4-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 551332dcf082833a5d3c1a27462c9bb3792fe42a
      
https://github.com/qemu/qemu/commit/551332dcf082833a5d3c1a27462c9bb3792fe42a
  Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/debug.c
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: Add itrigger_enabled field to CPURISCVState

Avoid calling riscv_itrigger_enabled() when calculate the tbflags.
As the itrigger enable status can only be changed when write
tdata1, migration load or itrigger fire, update env->itrigger_enabled
at these places.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-5-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e6ee9765a040a85a15b6c32ad553a9c40f9dfa1f
      
https://github.com/qemu/qemu/commit/e6ee9765a040a85a15b6c32ad553a9c40f9dfa1f
  Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/intc/sifive_plic.c

  Log Message:
  -----------
  hw/intc: sifive_plic: Renumber the S irqs for numa support

Commit 40244040a7a changed the way the S irqs are numbered. This breaks when
using numa configuration, e.g.:
./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
                      -m 2G -smp cpus=16 \
                      -object memory-backend-ram,id=mem0,size=512M \
                      -object memory-backend-ram,id=mem1,size=512M \
                      -object memory-backend-ram,id=mem2,size=512M \
                      -object memory-backend-ram,id=mem3,size=512M \
                      -numa node,cpus=0-3,memdev=mem0,nodeid=0 \
                      -numa node,cpus=4-7,memdev=mem1,nodeid=1 \
                      -numa node,cpus=8-11,memdev=mem2,nodeid=2 \
                      -numa node,cpus=12-15,memdev=mem3,nodeid=3
leads to:
Unexpected error in object_property_find_err() at ../qom/object.c:1304:
qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not
found

This patch makes the nubering of the S irqs identical to what it was before.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Message-Id: <20221114135122.1668703-1-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: eba06184f9a241a44ecce63cf0e52b8931b37853
      
https://github.com/qemu/qemu/commit/eba06184f9a241a44ecce63cf0e52b8931b37853
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Typo fix in sstc() predicate

We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.

Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0542709090383ff45fa9dbeb7bfe238dd96bf5e5
      
https://github.com/qemu/qemu/commit/0542709090383ff45fa9dbeb7bfe238dd96bf5e5
  Author: Atish Patra <atishp@rivosinc.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  hw/riscv: virt: Remove the redundant ipi-id property

The imsic DT binding[1] has changed and no longer require an ipi-id.
The latest IMSIC driver dynamically allocates ipi id if slow-ipi
is not defined.

Get rid of the unused dt property which may lead to confusion.

[1] 
https://lore.kernel.org/lkml/20221111044207.1478350-5-apatel@ventanamicro.com/

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221122080529.1692533-1-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 95dd4eb3b17ee4b010a9c6063c88fab8ed81095b
      
https://github.com/qemu/qemu/commit/95dd4eb3b17ee4b010a9c6063c88fab8ed81095b
  Author: Jim Shu <jim.shu@sifive.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: support cache-related PMU events in virtual mode

let tlb_fill() function also increments PMU counter when it is from
two-stage translation, so QEMU could also monitor these PMU events when
CPU runs in VS/VU mode (like running guest OS).

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221123090635.6574-1-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 507f33a47b24af38b8cfbd3a100856dc9e9d1fb4
      
https://github.com/qemu/qemu/commit/507f33a47b24af38b8cfbd3a100856dc9e9d1fb4
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()

sstatus register dump is currently missing in riscv_cpu_dump_state().
As sstatus is a copy of mstatus, which is described in the priv spec,
it seems redundant to print the same information twice.

Add some comments for this to let people know this is intentional.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221125050354.3166023-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 02b8fe08fb6749be5cc0cf83acf48fedc0e707bf
      
https://github.com/qemu/qemu/commit/02b8fe08fb6749be5cc0cf83acf48fedc0e707bf
  Author: Conor Dooley <conor.dooley@microchip.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/misc/mchp_pfsoc_ioscb.c
    M include/hw/misc/mchp_pfsoc_ioscb.h

  Log Message:
  -----------
  hw/misc: pfsoc: add fabric clocks to ioscb

On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by
"Clock Conditioning Circuitry" in the FPGA. The specific clock depends
on the FPGA bitstream & can be locked to one particular {D,P}LL - in the
Icicle Kit Reference Design v2022.09 or later this is/will be the case.

Linux v6.1+ will have a driver for this peripheral and devicetrees that
previously relied on "fixed-frequency" clock nodes have been switched
over to clock-controller nodes. The IOSCB region is represented in QEMU,
but the specific region of it that the CCCs occupy has not so v6.1-rcN
kernels fail to boot in QEMU.

Add the regions as unimplemented so that the status-quo in terms of boot
is maintained.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Message-Id: <20221117225518.4102575-2-conor@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1c3e1125096ff223d73e41502474fdd5783869bf
      
https://github.com/qemu/qemu/commit/1c3e1125096ff223d73e41502474fdd5783869bf
  Author: Conor Dooley <conor.dooley@microchip.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/riscv/microchip_pfsoc.c
    M include/hw/riscv/microchip_pfsoc.h

  Log Message:
  -----------
  hw/riscv: pfsoc: add missing FICs as unimplemented

The Fabric Interconnect Controllers provide interfaces between the FPGA
fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered
0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and
does not show up on the MSS memory map. FIC4 is dedicated to the User
Crypto Processor and does not show up on the MSS memory map either.

FIC 0, 1 & 3 do show up in the MSS memory map and neither FICs 0 or 1
are represented in QEMU, leading to load access violations while booting
Linux for Icicle if PCIe is enabled as the root port is connected via
either FIC 0 or 1.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Message-Id: <20221117225518.4102575-3-conor@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4889131a94498c8223513e2829a7b02d8e67ae81
      
https://github.com/qemu/qemu/commit/4889131a94498c8223513e2829a7b02d8e67ae81
  Author: Conor Dooley <conor.dooley@microchip.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/misc/mchp_pfsoc_ioscb.c
    M hw/misc/mchp_pfsoc_sysreg.c
    M hw/riscv/microchip_pfsoc.c
    M include/hw/misc/mchp_pfsoc_ioscb.h
    M include/hw/misc/mchp_pfsoc_sysreg.h
    M include/hw/riscv/microchip_pfsoc.h

  Log Message:
  -----------
  hw/{misc, riscv}: pfsoc: add system controller as unimplemented

The system controller on PolarFire SoC is access via a mailbox. The
control registers for this mailbox lie in the "IOSCB" region & the
interrupt is cleared via write to the "SYSREG" region. It also has a
QSPI controller, usually connected to a flash chip, that is used for
storing FPGA bitstreams and used for In-Application Programming (IAP).

Linux has an implementation of the system controller, through which the
hwrng is accessed, leading to load/store access faults.

Add the QSPI as unimplemented and a very basic (effectively
unimplemented) version of the system controller's mailbox. Rather than
purely marking the regions as unimplemented, service the mailbox
requests by reporting failures and raising the interrupt so a guest can
better handle the lack of support.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221117225518.4102575-4-conor@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 779c08f7fc3f5977f6cdb1ef301bc830609f8d48
      
https://github.com/qemu/qemu/commit/779c08f7fc3f5977f6cdb1ef301bc830609f8d48
  Author: Jim Shu <jim.shu@sifive.com>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/intc/sifive_plic.c

  Log Message:
  -----------
  hw/intc: sifive_plic: fix out-of-bound access of source_priority array

If the number of interrupt is not multiple of 32, PLIC will have
out-of-bound access to source_priority array. Compute the number of
interrupt in the last word to avoid this out-of-bound access of array.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20221127165753.30533-1-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 81a90d1ad090b72d2f7747bb18ff21875d028f34
      
https://github.com/qemu/qemu/commit/81a90d1ad090b72d2f7747bb18ff21875d028f34
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Fix mret exception cause when no pmp rule is configured

The priv spec v1.12 says:

  If no PMP entry matches an M-mode access, the access succeeds. If
  no PMP entry matches an S-mode or U-mode access, but at least one
  PMP entry is implemented, the access fails. Failed accesses generate
  an instruction, load, or store access-fault exception.

At present the exception cause is set to 'illegal instruction' but
should have been 'instruction access fault'.

Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP entry is 
configured")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221205065303.204095-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2d86fd5e3696ed9af7824687f33342d1aba925c9
      
https://github.com/qemu/qemu/commit/2d86fd5e3696ed9af7824687f33342d1aba925c9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/translate.c
    M tests/tcg/Makefile.target
    M tests/tcg/riscv64/Makefile.target
    A tests/tcg/riscv64/test-noc.S

  Log Message:
  -----------
  target/riscv: Set pc_succ_insn for !rvc illegal insn

Failure to set pc_succ_insn may result in a TB covering zero bytes,
which triggers an assert within the code generator.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org>
[ Changes by AF:
 - Add missing run-plugin-test-noc-% line
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 41e9dfcc5130ac78f5b24a155b2233dd6caf255f
      
https://github.com/qemu/qemu/commit/41e9dfcc5130ac78f5b24a155b2233dd6caf255f
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Simplify helper_sret() a little bit

There are 2 paths in helper_sret() and the same mstatus update codes
are replicated. Extract the common parts to simplify it a little bit.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221207090037.281452-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 498556f17b396f2f17ea8f3301e34bc8bd1b5af6
      
https://github.com/qemu/qemu/commit/498556f17b396f2f17ea8f3301e34bc8bd1b5af6
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+

Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when
leaving M-mode.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221207090037.281452-2-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 90296e06dd43e743c29bd22537d8d8ccf3e84ab5
      
https://github.com/qemu/qemu/commit/90296e06dd43e743c29bd22537d8d8ccf3e84ab5
  Author: Christoph Muellner <christoph.muellner@vrull.eu>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_rvzawrs.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  RISC-V: Add Zawrs ISA extension support

This patch adds support for the Zawrs ISA extension.
Given the current (incomplete) implementation of reservation sets
there seems to be no way to provide a full emulation of the WRS
instruction (wake on reservation set invalidation or timeout or
interrupt). Therefore, we just exit the TB and return to the main loop.

The specification can be found here:
  https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc

Note, that the Zawrs extension is frozen, but not ratified yet.

Changes since v3:
* Remove "RFC" since the extension is frozen
* Rebase on master and fix integration issues
* Fix entry ordering in extension list

Changes since v2:
* Rebase on master and resolve conflicts
* Adjustments according to a specification change
* Inline REQUIRE_ZAWRS() since it has only one user

Changes since v1:
* Adding zawrs to the ISA string that is passed to the kernel

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221005144948.3421504-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a89ec8445b65e6cf38499752e9695d05c595080a
      
https://github.com/qemu/qemu/commit/a89ec8445b65e6cf38499752e9695d05c595080a
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/intc/Kconfig
    M hw/riscv/Kconfig

  Log Message:
  -----------
  hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC

hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in sifive_plic_realize().

Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from
RISC-V machines.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <20221211030829.802437-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 27e64bb40188aea3fd8cb9d5176cc153a8e17c45
      
https://github.com/qemu/qemu/commit/27e64bb40188aea3fd8cb9d5176cc153a8e17c45
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/intc/Kconfig

  Log Message:
  -----------
  hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers

hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in both riscv_aplic_realize() and
riscv_imsic_realize().

Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221211030829.802437-2-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: aa2502459b9506bf6329b6aede9157e1f5b10022
      
https://github.com/qemu/qemu/commit/aa2502459b9506bf6329b6aede9157e1f5b10022
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/riscv/Kconfig

  Log Message:
  -----------
  hw/riscv: Fix opentitan dependency to SIFIVE_PLIC

Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build")
the IBEX PLIC model was replaced with the SiFive PLIC model in the
'opentitan' machine but we forgot the add the dependency there.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-3-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6c9a5417d35a24b68a0e655bce5ab1a885a35600
      
https://github.com/qemu/qemu/commit/6c9a5417d35a24b68a0e655bce5ab1a885a35600
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/riscv/Kconfig

  Log Message:
  -----------
  hw/riscv: Sort machines Kconfig options in alphabetical order

SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <20221211030829.802437-4-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1ab1954a0e478dd364e6f468bb42e5a1f11bf389
      
https://github.com/qemu/qemu/commit/1ab1954a0e478dd364e6f468bb42e5a1f11bf389
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/riscv/spike.c

  Log Message:
  -----------
  hw/riscv: spike: Remove misleading comments

PLIC is not included in the 'spike' machine.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-5-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 28d27684c1b06aca611b1e2f9165a18ac1fb7eb3
      
https://github.com/qemu/qemu/commit/28d27684c1b06aca611b1e2f9165a18ac1fb7eb3
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/intc/sifive_plic.c
    M include/hw/intc/sifive_plic.h

  Log Message:
  -----------
  hw/intc: sifive_plic: Drop PLICMode_H

H-mode has been removed since priv spec 1.10. Drop it.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-6-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e9a0866e5cffc3f9718f3a218343d3dead87638a
      
https://github.com/qemu/qemu/commit/e9a0866e5cffc3f9718f3a218343d3dead87638a
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/intc/sifive_plic.c

  Log Message:
  -----------
  hw/intc: sifive_plic: Improve robustness of the PLIC config parser

At present the PLIC config parser can only handle legal config string
like "MS,MS". However if a config string like ",MS,MS,,MS,MS,," is
given the parser won't get the correct configuration.

This commit improves the config parser to make it more robust.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-7-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ab705438eff3b3f5ac9592e0541a7c3a800bf590
      
https://github.com/qemu/qemu/commit/ab705438eff3b3f5ac9592e0541a7c3a800bf590
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/intc/sifive_plic.c

  Log Message:
  -----------
  hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in 
sifive_plic_realize()

The realize() callback has an errp for us to propagate the error up.
While we are here, correct the wrong multi-line comment format.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221211030829.802437-8-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: dd9ea8deb8a9dcd1814ada62d429b54d445169bd
      
https://github.com/qemu/qemu/commit/dd9ea8deb8a9dcd1814ada62d429b54d445169bd
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/intc/sifive_plic.c

  Log Message:
  -----------
  hw/intc: sifive_plic: Update "num-sources" property default value

At present the default value of "num-sources" property is zero,
which does not make a lot of sense, as in sifive_plic_realize()
we see s->bitfield_words is calculated by:

  s->bitfield_words = (s->num_sources + 31) >> 5;

if the we don't configure "num-sources" property its default value
zero makes s->bitfield_words zero too, which isn't true because
interrupt source 0 still occupies one word.

Let's change the default value to 1 meaning that only interrupt
source 0 is supported by default and a sanity check in realize().

While we are here, add a comment to describe the exact meaning of
this property that the number should include interrupt source 0.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-9-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a3751ce482cfde431ee0c9abfbe01af1c88f96af
      
https://github.com/qemu/qemu/commit/a3751ce482cfde431ee0c9abfbe01af1c88f96af
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M include/hw/riscv/microchip_pfsoc.h

  Log Message:
  -----------
  hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC

Per chapter 6.5.2 in [1], the number of interupt sources including
interrupt source 0 should be 187.

[1] PolarFire SoC MSS TRM:
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf

Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip PolarFire SoC 
Icicle Kit board")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Message-Id: <20221211030829.802437-10-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f800ba4a825f285580cf672cd497999e21cb3e7d
      
https://github.com/qemu/qemu/commit/f800ba4a825f285580cf672cd497999e21cb3e7d
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M include/hw/riscv/sifive_e.h

  Log Message:
  -----------
  hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC

Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003
supports 52 interrupt sources while G000 supports 51 interrupt sources.

We use the value of G002 and G003, so it is 53 (including source 0).

[1] G000 manual:
https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa4928c7_fe310-g000-manual-v3p2.pdf

[2] G002 manual:
https://sifive.cdn.prismic.io/sifive/034760b5-ac6a-4b1c-911c-f4148bb2c4a5_fe310-g002-v1p5.pdf

[3] G003 manual:
https://sifive.cdn.prismic.io/sifive/3af39c59-6498-471e-9dab-5355a0d539eb_fe310-g003-manual.pdf

Fixes: eb637edb1241 ("SiFive Freedom E Series RISC-V Machine")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-11-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 848f3638cd82542c2e70cd6d0b940d011b12b372
      
https://github.com/qemu/qemu/commit/848f3638cd82542c2e70cd6d0b940d011b12b372
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"

At present magic number is used to create "riscv,ndev" property
in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
is used to instantiate the PLIC model instead.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-12-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0a2054f8ef00a61bfa14fbeb92d0e117d54c7171
      
https://github.com/qemu/qemu/commit/0a2054f8ef00a61bfa14fbeb92d0e117d54c7171
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb

Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt 
machine")
changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which
is VIRTIO_NDEV and also used as the value of "riscv,ndev" property
in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM_SOURCES
should include interrupt source 0 but "riscv,ndev" does not.

While we are here, we also fix the comments of platform bus irq range
which is now "64 to 96", but should be "64 to 95", introduced since
commit 1832b7cb3f64 ("hw/riscv: virt: Create a platform bus").

Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt 
machine")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-13-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 612675d39773e763c1b6f44f73e87cbe8ce3d4a9
      
https://github.com/qemu/qemu/commit/612675d39773e763c1b6f44f73e87cbe8ce3d4a9
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/intc/sifive_plic.c
    M include/hw/riscv/microchip_pfsoc.h
    M include/hw/riscv/shakti_c.h
    M include/hw/riscv/sifive_e.h
    M include/hw/riscv/sifive_u.h
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0

At present the SiFive PLIC model "priority-base" expects interrupt
priority register base starting from source 1 instead source 0,
that's why on most platforms "priority-base" is set to 0x04 except
'opentitan' machine. 'opentitan' should have set "priority-base"
to 0x04 too.

Note the irq number calculation in sifive_plic_{read,write} is
correct as the codes make up for the irq number by adding 1.

Let's simply update "priority-base" to start from interrupt source
0 and add a comment to make it crystal clear.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <20221211030829.802437-14-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 65fb815f3aac7a450ecaa1c7c5be1123bd24ee0a
      
https://github.com/qemu/qemu/commit/65fb815f3aac7a450ecaa1c7c5be1123bd24ee0a
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/riscv/opentitan.c

  Log Message:
  -----------
  hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization

"hartid-base" and "priority-base" are zero by default. There is no
need to initialize them to zero again.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-15-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 71a9bc59728a054036f3db7dd82dab8f8bd2baf9
      
https://github.com/qemu/qemu/commit/71a9bc59728a054036f3db7dd82dab8f8bd2baf9
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2022-12-22 (Thu, 22 Dec 2022)

  Changed paths:
    M hw/intc/sifive_plic.c

  Log Message:
  -----------
  hw/intc: sifive_plic: Fix the pending register range check

The pending register upper limit is currently set to
plic->num_sources >> 3, which is wrong, e.g.: considering
plic->num_sources is 7, the upper limit becomes 0 which fails
the range check if reading the pending register at pending_base.

Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-16-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7f520b12fdbcc08c9076500ca793e85f9f54b454
      
https://github.com/qemu/qemu/commit/7f520b12fdbcc08c9076500ca793e85f9f54b454
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-01-03 (Tue, 03 Jan 2023)

  Changed paths:
    M hw/intc/Kconfig
    M hw/intc/sifive_plic.c
    M hw/misc/mchp_pfsoc_ioscb.c
    M hw/misc/mchp_pfsoc_sysreg.c
    M hw/riscv/Kconfig
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M hw/ssi/ibex_spi_host.c
    M include/hw/intc/sifive_plic.h
    M include/hw/misc/mchp_pfsoc_ioscb.h
    M include/hw/misc/mchp_pfsoc_sysreg.h
    M include/hw/registerfields.h
    M include/hw/riscv/microchip_pfsoc.h
    M include/hw/riscv/opentitan.h
    M include/hw/riscv/shakti_c.h
    M include/hw/riscv/sifive_e.h
    M include/hw/riscv/sifive_u.h
    M include/hw/riscv/virt.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/debug.c
    M target/riscv/debug.h
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_privileged.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    A target/riscv/insn_trans/trans_rvzawrs.c.inc
    M target/riscv/machine.c
    M target/riscv/op_helper.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h
    M target/riscv/translate.c
    M tcg/riscv/tcg-target.c.inc
    M tests/tcg/Makefile.target
    M tests/tcg/riscv64/Makefile.target
    A tests/tcg/riscv64/test-noc.S

  Log Message:
  -----------
  Merge tag 'pull-riscv-to-apply-20221222-1' of 
https://github.com/alistair23/qemu into staging

First RISC-V PR for QEMU 8.0

* Fix PMP propagation for tlb
* Collection of bug fixes
* Add the `FIELDx_1CLEAR()` macro
* Bump the OpenTitan supported version
* Add smstateen support
* Support native debug icount trigger
* Remove the redundant ipi-id property in the virt machine
* Support cache-related PMU events in virtual mode
* Add some missing PolarFire SoC io regions
* Fix mret exception cause when no pmp rule is configured
* Fix bug where disabling compressed instructions would crash QEMU
* Add Zawrs ISA extension support
* A range of code refactoring and cleanups

# gpg: Signature made Wed 21 Dec 2022 22:39:37 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20221222-1' of https://github.com/alistair23/qemu: 
(45 commits)
  hw/intc: sifive_plic: Fix the pending register range check
  hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
  hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
  hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
  hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
  hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
  hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
  hw/intc: sifive_plic: Update "num-sources" property default value
  hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in 
sifive_plic_realize()
  hw/intc: sifive_plic: Improve robustness of the PLIC config parser
  hw/intc: sifive_plic: Drop PLICMode_H
  hw/riscv: spike: Remove misleading comments
  hw/riscv: Sort machines Kconfig options in alphabetical order
  hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
  hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
  hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
  RISC-V: Add Zawrs ISA extension support
  target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
  target/riscv: Simplify helper_sret() a little bit
  target/riscv: Set pc_succ_insn for !rvc illegal insn
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/2782f45985cb...7f520b12fdbc
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