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[Qemu-commits] [qemu/qemu] 9e65f4: target/arm:Set lg_page_size to 0 if e
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 9e65f4: target/arm:Set lg_page_size to 0 if either S1 or S... |
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Date: |
Fri, 06 Jan 2023 03:55:53 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 9e65f4e6da56e1c21af9f877e29d9db3a243b7f9
https://github.com/qemu/qemu/commit/9e65f4e6da56e1c21af9f877e29d9db3a243b7f9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm:Set lg_page_size to 0 if either S1 or S2 asks for it
In get_phys_addr_twostage() we set the lg_page_size of the result to
the maximum of the stage 1 and stage 2 page sizes. This works for
the case where we do want to create a TLB entry, because we know the
common TLB code only creates entries of the TARGET_PAGE_SIZE and
asking for a size larger than that only means that invalidations
invalidate the whole larger area. However, if lg_page_size is
smaller than TARGET_PAGE_SIZE this effectively means "don't create a
TLB entry"; in this case if either S1 or S2 said "this covers less
than a page and can't go in a TLB" then the final result also should
be marked that way. Set the resulting page size to 0 if either
stage asked for a less-than-a-page entry, and expand the comment
to explain what's going on.
This has no effect for VMSA because currently the VMSA lookup always
returns results that cover at least TARGET_PAGE_SIZE; however when we
add v8R support it will reuse this code path, and for v8R the S1 and
S2 results can be smaller than TARGET_PAGE_SIZE.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221212142708.610090-1-peter.maydell@linaro.org
Commit: c7f786abe2eb2f57d363e76ff992de863e998e1e
https://github.com/qemu/qemu/commit/c7f786abe2eb2f57d363e76ff992de863e998e1e
Author: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Don't add all MIDR aliases for cores that implement PMSA
Cores with PMSA have the MPUIR register which has the
same encoding as the MIDR alias with opc2=4. So we only
add that alias if we are not realizing a core that
implements PMSA.
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221206102504.165775-2-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 910e4f24975f53645d308aa6c895f4599dd47c43
https://github.com/qemu/qemu/commit/910e4f24975f53645d308aa6c895f4599dd47c43
Author: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/cpu.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Make RVBAR available for all ARMv8 CPUs
RVBAR shadows RVBAR_ELx where x is the highest exception
level if the highest EL is not EL3. This patch also allows
ARMv8 CPUs to change the reset address with
the rvbar property.
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-3-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: faa1451e7b6443d0bc23099886626a4b6f91301f
https://github.com/qemu/qemu/commit/faa1451e7b6443d0bc23099886626a4b6f91301f
Author: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Make stage_2_format for cache attributes optional
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
VMSAv8, the stage 2 attributes are in the same format as the stage 1
attributes (8-bit MAIR format). Rather than converting the MAIR
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
stage 2 descriptor) and then converting back to do the attribute
combination, allow combined_attrs_nofwb() to accept s2 attributes
that are already in the MAIR format.
We move the assert() to combined_attrs_fwb(), because that function
really does require a VMSA stage 2 attribute format. (We will never
get there for v8R, because PMSAv8 does not implement FEAT_S2FWB.)
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-4-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 452c67a427047728a9a7f87695024f08e4dfd3bf
https://github.com/qemu/qemu/commit/452c67a427047728a9a7f87695024f08e4dfd3bf
Author: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/debug_helper.c
M target/arm/internals.h
M target/arm/tlb_helper.c
Log Message:
-----------
target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
tough they don't have the TTBCR register.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-5-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 761c46425e2d2a7a65cbbd1ee65f0abce769618c
https://github.com/qemu/qemu/commit/761c46425e2d2a7a65cbbd1ee65f0abce769618c
Author: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Add PMSAv8r registers
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fca45e3467f7cb701333139eab65886c2f438f8a
https://github.com/qemu/qemu/commit/fca45e3467f7cb701333139eab65886c2f438f8a
Author: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Add PMSAv8r functionality
Add PMSAv8r translation.
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-7-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5f536d01d1141a56f5057b62c82fa94826d367f0
https://github.com/qemu/qemu/commit/5f536d01d1141a56f5057b62c82fa94826d367f0
Author: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Add ARM Cortex-R52 CPU
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-8-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9788d4c007cbde7cda1b7a577b8b836335eb2b73
https://github.com/qemu/qemu/commit/9788d4c007cbde7cda1b7a577b8b836335eb2b73
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: fix handling of HLT semihosting in system mode
The check semihosting_enabled() wants to know if the guest is
currently in user mode. Unlike the other cases the test was inverted
causing us to block semihosting calls in non-EL0 modes.
Cc: qemu-stable@nongnu.org
Fixes: 19b26317e9 (target/arm: Honour -semihosting-config userspace=on)
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b9c993aaf8962a99bc6da80918e30d582912c863
https://github.com/qemu/qemu/commit/b9c993aaf8962a99bc6da80918e30d582912c863
Author: Axel Heider <axel.heider@hensoldt.net>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/timer/imx_epit.c
Log Message:
-----------
hw/timer/imx_epit: improve comments
Fix typos, add background information
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 018ee7948ff1df9cd98efee6e9d117eadb630cff
https://github.com/qemu/qemu/commit/018ee7948ff1df9cd98efee6e9d117eadb630cff
Author: Axel Heider <axel.heider@hensoldt.net>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/timer/imx_epit.c
M include/hw/timer/imx_epit.h
Log Message:
-----------
hw/timer/imx_epit: cleanup CR defines
remove unused defines, add needed defines
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1ead962edf1297e223a039167429d4c986bfb90e
https://github.com/qemu/qemu/commit/1ead962edf1297e223a039167429d4c986bfb90e
Author: Axel Heider <axel.heider@hensoldt.net>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/timer/imx_epit.c
M include/hw/timer/imx_epit.h
Log Message:
-----------
hw/timer/imx_epit: define SR_OCIF
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2ca267fd36a275c771528bd5ae50ae8406155ad9
https://github.com/qemu/qemu/commit/2ca267fd36a275c771528bd5ae50ae8406155ad9
Author: Axel Heider <axel.heider@hensoldt.net>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/timer/imx_epit.c
Log Message:
-----------
hw/timer/imx_epit: update interrupt state on CR write access
The interrupt state can change due to:
- reset clears both SR.OCIF and CR.OCIE
- write to CR.EN or CR.OCIE
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3d4615812578ca9f120e6e42237c90f56ca6db87
https://github.com/qemu/qemu/commit/3d4615812578ca9f120e6e42237c90f56ca6db87
Author: Axel Heider <axel.heider@hensoldt.net>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/timer/imx_epit.c
Log Message:
-----------
hw/timer/imx_epit: hard reset initializes CR with 0
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 793a6ea0753562ab74ef86617415d3b50b9ec308
https://github.com/qemu/qemu/commit/793a6ea0753562ab74ef86617415d3b50b9ec308
Author: Axel Heider <axel.heider@hensoldt.net>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/timer/imx_epit.c
Log Message:
-----------
hw/timer/imx_epit: factor out register write handlers
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e662449aa670bff938a011220593dd059b75e84b
https://github.com/qemu/qemu/commit/e662449aa670bff938a011220593dd059b75e84b
Author: Axel Heider <axel.heider@hensoldt.net>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/timer/imx_epit.c
M include/hw/timer/imx_epit.h
Log Message:
-----------
hw/timer/imx_epit: remove explicit fields cnt and freq
The CNT register is a read-only register. There is no need to
store it's value, it can be calculated on demand.
The calculated frequency is needed temporarily only.
Note that this is a migration compatibility break for all boards
types that use the EPIT peripheral.
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8d71beaf1e6b49266c4d98286f4ce6c874c998ae
https://github.com/qemu/qemu/commit/8d71beaf1e6b49266c4d98286f4ce6c874c998ae
Author: Axel Heider <axel.heider@hensoldt.net>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/timer/imx_epit.c
Log Message:
-----------
hw/timer/imx_epit: fix compare timer handling
- fix #1263 for CR writes
- rework compare time handling
- The compare timer has to run even if CR.OCIEN is not set,
as SR.OCIF must be updated.
- The compare timer fires exactly once when the
compare value is less than the current value, but the
reload values is less than the compare value.
- The compare timer will never fire if the reload value is
less than the compare value. Disable it in this case.
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
[PMM: fixed minor style nits]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9b37a28c78376b93eea209eaa052d7c6c7a579ba
https://github.com/qemu/qemu/commit/9b37a28c78376b93eea209eaa052d7c6c7a579ba
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix checkpatch comment style warnings in helper.c
Fix these:
WARNING: Block comments use a leading /* on a separate line
WARNING: Block comments use * on subsequent lines
WARNING: Block comments use a trailing */ on a separate line
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-2-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 04215eb100e940b35b48956376ea6565d3e78393
https://github.com/qemu/qemu/commit/04215eb100e940b35b48956376ea6565d3e78393
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix checkpatch space errors in helper.c
Fix the following:
ERROR: spaces required around that '|' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: spaces required around that '+' (ctx:VxB)
ERROR: space prohibited between function name and open parenthesis '('
(the last two still have some occurrences in macros which I left
behind because it might impact readability)
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-3-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f927dbda86b2532049df45b2174ce05919517699
https://github.com/qemu/qemu/commit/f927dbda86b2532049df45b2174ce05919517699
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix checkpatch brace errors in helper.c
Fix this:
ERROR: braces {} are necessary for all arms of this statement
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-4-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c6675a857c786421c41023610672d8aed9e02d37
https://github.com/qemu/qemu/commit/c6675a857c786421c41023610672d8aed9e02d37
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/m_helper.c
Log Message:
-----------
target/arm: Remove unused includes from m_helper.c
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-5-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cdfea280b358ddc42d582562475c36c5564bf2b2
https://github.com/qemu/qemu/commit/cdfea280b358ddc42d582562475c36c5564bf2b2
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Remove unused includes from helper.c
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-6-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: edd2dc4e3a15e9aa6a759fc8478999215ff1be53
https://github.com/qemu/qemu/commit/edd2dc4e3a15e9aa6a759fc8478999215ff1be53
Author: Claudio Fontana <cfontana@suse.de>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu64.c
Log Message:
-----------
target/arm: cleanup cpu includes
Remove some unused headers.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20221213190537.511-7-farosas@suse.de
[added back some includes that are still needed at this point]
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3d153708943c176befe6712e37b580d4287eba6f
https://github.com/qemu/qemu/commit/3d153708943c176befe6712e37b580d4287eba6f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/input/tsc2005.c
M hw/input/tsc210x.c
M include/hw/input/tsc2xxx.h
Log Message:
-----------
hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg
The pointed MouseTransformInfo structure is accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221220142520.24094-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bd8d01bf57335dd6c369e220910ee3e4c4fe3fea
https://github.com/qemu/qemu/commit/bd8d01bf57335dd6c369e220910ee3e4c4fe3fea
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/arm/nseries.c
Log Message:
-----------
hw/arm/nseries: Constify various read-only arrays
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221220142520.24094-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6aee34000eab02409c6925ebe6e046c2a3b800fc
https://github.com/qemu/qemu/commit/6aee34000eab02409c6925ebe6e046c2a3b800fc
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/arm/nseries.c
Log Message:
-----------
hw/arm/nseries: Silent -Wmissing-field-initializers warning
Silent when compiling with -Wextra:
../hw/arm/nseries.c:1081:12: warning: missing field 'line' initializer
[-Wmissing-field-initializers]
{ NULL }
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221220142520.24094-4-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bc6bd20ee3538347afb750c4bd06edca4a922897
https://github.com/qemu/qemu/commit/bc6bd20ee3538347afb750c4bd06edca4a922897
Author: Zhuojia Shen <chaosdefinition@hotmail.com>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M target/arm/helper.c
M tests/tcg/aarch64/Makefile.target
M tests/tcg/aarch64/sysregs.c
Log Message:
-----------
target/arm: align exposed ID registers with Linux
In CPUID registers exposed to userspace, some registers were missing
and some fields were not exposed. This patch aligns exposed ID
registers and their fields with what the upstream kernel currently
exposes.
Specifically, the following new ID registers/fields are exposed to
userspace:
ID_AA64PFR1_EL1.BT: bits 3-0
ID_AA64PFR1_EL1.MTE: bits 11-8
ID_AA64PFR1_EL1.SME: bits 27-24
ID_AA64ZFR0_EL1.SVEver: bits 3-0
ID_AA64ZFR0_EL1.AES: bits 7-4
ID_AA64ZFR0_EL1.BitPerm: bits 19-16
ID_AA64ZFR0_EL1.BF16: bits 23-20
ID_AA64ZFR0_EL1.SHA3: bits 35-32
ID_AA64ZFR0_EL1.SM4: bits 43-40
ID_AA64ZFR0_EL1.I8MM: bits 47-44
ID_AA64ZFR0_EL1.F32MM: bits 55-52
ID_AA64ZFR0_EL1.F64MM: bits 59-56
ID_AA64SMFR0_EL1.F32F32: bit 32
ID_AA64SMFR0_EL1.B16F32: bit 34
ID_AA64SMFR0_EL1.F16F32: bit 35
ID_AA64SMFR0_EL1.I8I32: bits 39-36
ID_AA64SMFR0_EL1.F64F64: bit 48
ID_AA64SMFR0_EL1.I16I64: bits 55-52
ID_AA64SMFR0_EL1.FA64: bit 63
ID_AA64MMFR0_EL1.ECV: bits 63-60
ID_AA64MMFR1_EL1.AFP: bits 47-44
ID_AA64MMFR2_EL1.AT: bits 35-32
ID_AA64ISAR0_EL1.RNDR: bits 63-60
ID_AA64ISAR1_EL1.FRINTTS: bits 35-32
ID_AA64ISAR1_EL1.BF16: bits 47-44
ID_AA64ISAR1_EL1.DGH: bits 51-48
ID_AA64ISAR1_EL1.I8MM: bits 55-52
ID_AA64ISAR2_EL1.WFxT: bits 3-0
ID_AA64ISAR2_EL1.RPRES: bits 7-4
ID_AA64ISAR2_EL1.GPA3: bits 11-8
ID_AA64ISAR2_EL1.APA3: bits 15-12
The code is also refactored to use symbolic names for ID register fields
for better readability and maintainability.
The test case in tests/tcg/aarch64/sysregs.c is also updated to match
the intended behavior.
Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
Message-id:
DS7PR12MB6309FB585E10772928F14271ACE79@DS7PR12MB6309.namprd12.prod.outlook.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: use Sn_n_Cn_Cn_n syntax to work with older assemblers
that don't recognize id_aa64isar2_el1 and id_aa64mmfr2_el1]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1e793dd69680a42d3d4ea25450e006322817e0dd
https://github.com/qemu/qemu/commit/1e793dd69680a42d3d4ea25450e006322817e0dd
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/arm/smmu-common.c
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope
This function is not used anywhere outside this file,
so we can make the function "static void".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20221216214924.4711-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9de9fa5cf2b26b13e895516c6fa1671af6994a6a
https://github.com/qemu/qemu/commit/9de9fa5cf2b26b13e895516c6fa1671af6994a6a
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/arm/smmu-common.c
Log Message:
-----------
hw/arm/smmu-common: Avoid using inlined functions with external linkage
When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)")
and building with -Wall we get:
hw/arm/smmu-common.c:173:33: warning: static function
'smmu_hash_remove_by_asid_iova' is used in an inline function with external
linkage [-Wstatic-in-inline]
hw/arm/smmu-common.h:170:1: note: use 'static' to give inline function
'smmu_iotlb_inv_iova' internal linkage
void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
^
static
None of our code base require / use inlined functions with external
linkage. Some places use internal inlining in the hot path. These
two functions are certainly not in any hot path and don't justify
any inlining, so these are likely oversights rather than intentional.
Reported-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20221216214924.4711-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 60c98e72055f6ae944b459a7c0c53962caaba269
https://github.com/qemu/qemu/commit/60c98e72055f6ae944b459a7c0c53962caaba269
Author: Jean-Christophe Dubois <jcd@tribudubois.net>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/arm/fsl-imx7.c
M include/hw/arm/fsl-imx7.h
Log Message:
-----------
i.MX7D: Connect GPT timers to IRQ
So far the GPT timers were unable to raise IRQs to the processor.
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 111c4c49c3d5db20d7cac754f486f3989ac00c08
https://github.com/qemu/qemu/commit/111c4c49c3d5db20d7cac754f486f3989ac00c08
Author: Jean-Christophe Dubois <jcd@tribudubois.net>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/misc/imx7_ccm.c
Log Message:
-----------
i.MX7D: Compute clock frequency for the fixed frequency clocks.
CCM derived clocks will have to be added later.
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a1e03956f4fb355d33a8a4d9f23ed35ccbed9ec9
https://github.com/qemu/qemu/commit/a1e03956f4fb355d33a8a4d9f23ed35ccbed9ec9
Author: Jean-Christophe Dubois <jcd@tribudubois.net>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/arm/fsl-imx6ul.c
M hw/misc/imx6ul_ccm.c
M hw/timer/imx_gpt.c
M include/hw/timer/imx_gpt.h
Log Message:
-----------
i.MX6UL: Add a specific GPT timer instance for the i.MX6UL
The i.MX6UL doesn't support CLK_HIGH ou CLK_HIGH_DIV clock source.
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c73c2798304916a27c21157bbc24acccdeb3c5e2
https://github.com/qemu/qemu/commit/c73c2798304916a27c21157bbc24acccdeb3c5e2
Author: Jean-Christophe Dubois <jcd@tribudubois.net>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/arm/fsl-imx7.c
M include/hw/arm/fsl-imx7.h
Log Message:
-----------
i.MX7D: Connect IRQs to GPIO devices.
IRQs were not associated to the various GPIO devices inside i.MX7D.
This patch brings the i.MX7D on par with i.MX6.
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 20221226101418.415170-1-jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 93c9678de9dc7d2e68f9e8477da072bac30ef132
https://github.com/qemu/qemu/commit/93c9678de9dc7d2e68f9e8477da072bac30ef132
Author: Stephen Longfield <slongfield@google.com>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/net/imx_fec.c
Log Message:
-----------
hw/net: Fix read of uninitialized memory in imx_fec.
Size is used at lines 1088/1188 for the loop, which reads the last 4
bytes from the crc_ptr so it does need to get increased, however it
shouldn't be increased before the buffer is passed to CRC computation,
or the crc32 function will access uninitialized memory.
This was pointed out to me by clg@kaod.org during the code review of
a similar patch to hw/net/ftgmac100.c
Change-Id: Ib0464303b191af1e28abeb2f5105eb25aadb5e9b
Signed-off-by: Stephen Longfield <slongfield@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Message-id: 20221221183202.3788132-1-slongfield@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d365cb0b9d14eb562ce85d3acfe36e8aad13df3f
https://github.com/qemu/qemu/commit/d365cb0b9d14eb562ce85d3acfe36e8aad13df3f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-01-05 (Thu, 05 Jan 2023)
Changed paths:
M hw/arm/fsl-imx6ul.c
M hw/arm/fsl-imx7.c
M hw/arm/nseries.c
M hw/arm/smmu-common.c
M hw/input/tsc2005.c
M hw/input/tsc210x.c
M hw/misc/imx6ul_ccm.c
M hw/misc/imx7_ccm.c
M hw/net/imx_fec.c
M hw/timer/imx_epit.c
M hw/timer/imx_gpt.c
M include/hw/arm/fsl-imx7.h
M include/hw/arm/smmu-common.h
M include/hw/input/tsc2xxx.h
M include/hw/timer/imx_epit.h
M include/hw/timer/imx_gpt.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/debug_helper.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/m_helper.c
M target/arm/machine.c
M target/arm/ptw.c
M target/arm/tlb_helper.c
M target/arm/translate.c
M tests/tcg/aarch64/Makefile.target
M tests/tcg/aarch64/sysregs.c
Log Message:
-----------
Merge tag 'pull-target-arm-20230105' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Implement AArch32 ARMv8-R support
* Add Cortex-R52 CPU
* fix handling of HLT semihosting in system mode
* hw/timer/ixm_epit: cleanup and fix bug in compare handling
* target/arm: Coding style fixes
* target/arm: Clean up includes
* nseries: minor code cleanups
* target/arm: align exposed ID registers with Linux
* hw/arm/smmu-common: remove unnecessary inlines
* i.MX7D: Handle GPT timers
* i.MX7D: Connect IRQs to GPIO devices
* i.MX6UL: Add a specific GPT timer instance
* hw/net: Fix read of uninitialized memory in imx_fec
# gpg: Signature made Thu 05 Jan 2023 16:43:18 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20230105' of
https://git.linaro.org/people/pmaydell/qemu-arm: (34 commits)
hw/net: Fix read of uninitialized memory in imx_fec.
i.MX7D: Connect IRQs to GPIO devices.
i.MX6UL: Add a specific GPT timer instance for the i.MX6UL
i.MX7D: Compute clock frequency for the fixed frequency clocks.
i.MX7D: Connect GPT timers to IRQ
hw/arm/smmu-common: Avoid using inlined functions with external linkage
hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope
target/arm: align exposed ID registers with Linux
hw/arm/nseries: Silent -Wmissing-field-initializers warning
hw/arm/nseries: Constify various read-only arrays
hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg
target/arm: cleanup cpu includes
target/arm: Remove unused includes from helper.c
target/arm: Remove unused includes from m_helper.c
target/arm: Fix checkpatch brace errors in helper.c
target/arm: Fix checkpatch space errors in helper.c
target/arm: Fix checkpatch comment style warnings in helper.c
hw/timer/imx_epit: fix compare timer handling
hw/timer/imx_epit: remove explicit fields cnt and freq
hw/timer/imx_epit: factor out register write handlers
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/d1852caab131...d365cb0b9d14