[Qemu-devel] [PULL 035/118] target-ppc: Introduce DFP Compares

[Alexander Graf]

From: Tom Musta <address@hidden>

Add emulation of the PowerPC Decimal Floating Point Compare instructions
dcmpu[q] and dcmpo[q].

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
 target-ppc/dfp_helper.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++
 target-ppc/helper.h     |  4 ++++
 target-ppc/translate.c  |  8 +++++++
 3 files changed, 70 insertions(+)

diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c
index 2dca9d4..1816f44 100644
--- a/target-ppc/dfp_helper.c
+++ b/target-ppc/dfp_helper.c
@@ -294,6 +294,32 @@ static void dfp_check_for_VXIDI(struct PPC_DFP *dfp)
     }
 }
 
+static void dfp_check_for_VXVC(struct PPC_DFP *dfp)
+{
+    if (decNumberIsNaN(&dfp->a) || decNumberIsNaN(&dfp->b)) {
+        dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXVC, FP_VE);
+    }
+}
+
+static void dfp_set_CRBF_from_T(struct PPC_DFP *dfp)
+{
+    if (decNumberIsNaN(&dfp->t)) {
+        dfp->crbf = 1;
+    } else if (decNumberIsZero(&dfp->t)) {
+        dfp->crbf = 2;
+    } else if (decNumberIsNegative(&dfp->t)) {
+        dfp->crbf = 8;
+    } else {
+        dfp->crbf = 4;
+    }
+}
+
+static void dfp_set_FPCC_from_CRBF(struct PPC_DFP *dfp)
+{
+    dfp->env->fpscr &= ~(0xF << 12);
+    dfp->env->fpscr |= (dfp->crbf << 12);
+}
+
 #define DFP_HELPER_TAB(op, dnop, postprocs, size)                              
\
 void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *a, uint64_t *b)      
\
 {                                                                              
\
@@ -363,3 +389,35 @@ static void DIV_PPs(struct PPC_DFP *dfp)
 
 DFP_HELPER_TAB(ddiv, decNumberDivide, DIV_PPs, 64)
 DFP_HELPER_TAB(ddivq, decNumberDivide, DIV_PPs, 128)
+
+#define DFP_HELPER_BF_AB(op, dnop, postprocs, size)                            
\
+uint32_t helper_##op(CPUPPCState *env, uint64_t *a, uint64_t *b)               
\
+{                                                                              
\
+    struct PPC_DFP dfp;                                                        
\
+    dfp_prepare_decimal##size(&dfp, a, b, env);                                
\
+    dnop(&dfp.t, &dfp.a, &dfp.b, &dfp.context);                                
\
+    decimal##size##FromNumber((decimal##size *)dfp.t64, &dfp.t, &dfp.context); 
\
+    postprocs(&dfp);                                                           
\
+    return dfp.crbf;                                                           
\
+}
+
+static void CMPU_PPs(struct PPC_DFP *dfp)
+{
+    dfp_set_CRBF_from_T(dfp);
+    dfp_set_FPCC_from_CRBF(dfp);
+    dfp_check_for_VXSNAN(dfp);
+}
+
+DFP_HELPER_BF_AB(dcmpu, decNumberCompare, CMPU_PPs, 64)
+DFP_HELPER_BF_AB(dcmpuq, decNumberCompare, CMPU_PPs, 128)
+
+static void CMPO_PPs(struct PPC_DFP *dfp)
+{
+    dfp_set_CRBF_from_T(dfp);
+    dfp_set_FPCC_from_CRBF(dfp);
+    dfp_check_for_VXSNAN(dfp);
+    dfp_check_for_VXVC(dfp);
+}
+
+DFP_HELPER_BF_AB(dcmpo, decNumberCompare, CMPO_PPs, 64)
+DFP_HELPER_BF_AB(dcmpoq, decNumberCompare, CMPO_PPs, 128)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index f0c0306..2bbae63 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -624,3 +624,7 @@ DEF_HELPER_4(dmul, void, env, fprp, fprp, fprp)
 DEF_HELPER_4(dmulq, void, env, fprp, fprp, fprp)
 DEF_HELPER_4(ddiv, void, env, fprp, fprp, fprp)
 DEF_HELPER_4(ddivq, void, env, fprp, fprp, fprp)
+DEF_HELPER_3(dcmpo, i32, env, fprp, fprp)
+DEF_HELPER_3(dcmpoq, i32, env, fprp, fprp)
+DEF_HELPER_3(dcmpu, i32, env, fprp, fprp)
+DEF_HELPER_3(dcmpuq, i32, env, fprp, fprp)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 56d331e..e708640 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -8363,6 +8363,10 @@ GEN_DFP_T_A_B_Rc(dmul)
 GEN_DFP_T_A_B_Rc(dmulq)
 GEN_DFP_T_A_B_Rc(ddiv)
 GEN_DFP_T_A_B_Rc(ddivq)
+GEN_DFP_BF_A_B(dcmpu)
+GEN_DFP_BF_A_B(dcmpuq)
+GEN_DFP_BF_A_B(dcmpo)
+GEN_DFP_BF_A_B(dcmpoq)
 /***                           SPE extension                               ***/
 /* Register moves */
 
@@ -11298,6 +11302,10 @@ GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
+GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
+GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
+GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
+GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
 #undef GEN_SPE
 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
     GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, 
PPC_NONE)
-- 
1.8.1.4