[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v3 01/16] target/riscv: cpu: Add a new 'resetvec' property
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v3 01/16] target/riscv: cpu: Add a new 'resetvec' property |
Date: |
Tue, 1 Sep 2020 11:36:56 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 |
On 9/1/20 3:38 AM, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
>
> Currently the reset vector address is hard-coded in a RISC-V CPU's
> instance_init() routine. In a real world we can have 2 exact same
> CPUs except for the reset vector address, which is pretty common in
> the RISC-V core IP licensing business.
>
> Normally reset vector address is a configurable parameter. Let's
> create a 64-bit property to store the reset vector address which
> covers both 32-bit and 64-bit CPUs.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v1)
>
> target/riscv/cpu.h | 1 +
> target/riscv/cpu.c | 1 +
> 2 files changed, 2 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- Re: [PATCH v3 01/16] target/riscv: cpu: Add a new 'resetvec' property,
Philippe Mathieu-Daudé <=