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Re: [PATCH v3 02/16] hw/riscv: hart: Add a new 'resetvec' property
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v3 02/16] hw/riscv: hart: Add a new 'resetvec' property |
Date: |
Tue, 1 Sep 2020 11:37:10 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 |
On 9/1/20 3:38 AM, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
>
> RISC-V machines do not instantiate RISC-V CPUs directly, instead
> they do that via the hart array. Add a new property for the reset
> vector address to allow the value to be passed to the CPU, before
> CPU is realized.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v1)
>
> include/hw/riscv/riscv_hart.h | 1 +
> hw/riscv/riscv_hart.c | 3 +++
> 2 files changed, 4 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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