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[PULL 02/47] target/arm: Use correct ID register check for aa32_fp16_ari
From: |
Peter Maydell |
Subject: |
[PULL 02/47] target/arm: Use correct ID register check for aa32_fp16_arith |
Date: |
Tue, 1 Sep 2020 16:17:38 +0100 |
The aa32_fp16_arith feature check function currently looks at the
AArch64 ID_AA64PFR0 register. This is (as the comment notes) not
correct. The bogus check was put in mostly to allow testing of the
fp16 variants of the VCMLA instructions and it was something of
a mistake that we allowed them to exist in master.
Switch the feature check function to testing VMFR1.FPHP, which is
what it ought to be.
This will remove emulation of the VCMLA and VCADD insns from
AArch32 code running on an AArch64 '-cpu max' using system emulation.
(They were never enabled for aarch32 linux-user and system-emulation.)
Since we weren't advertising their existence via the AArch32 ID
register, well-behaved guests wouldn't have been using them anyway.
Once we have implemented all the AArch32 support for the FP16 extension
we will advertise it in the MVFR1 ID register field, which will reenable
these insns along with all the others.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-3-peter.maydell@linaro.org
---
target/arm/cpu.h | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ac857bdc2c1..a1c7d8ebae5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3519,12 +3519,7 @@ static inline bool isar_feature_aa32_predinv(const
ARMISARegisters *id)
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
{
- /*
- * This is a placeholder for use by VCMA until the rest of
- * the ARMv8.2-FP16 extension is implemented for aa32 mode.
- * At which point we can properly set and check MVFR1.FPHP.
- */
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
}
static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
--
2.20.1
- [PULL 00/47] target-arm queue, Peter Maydell, 2020/09/01
- [PULL 01/47] target/arm: Remove local definitions of float constants, Peter Maydell, 2020/09/01
- [PULL 02/47] target/arm: Use correct ID register check for aa32_fp16_arith,
Peter Maydell <=
- [PULL 03/47] target/arm: Implement VFP fp16 for VFP_BINOP operations, Peter Maydell, 2020/09/01
- [PULL 05/47] target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS, Peter Maydell, 2020/09/01
- [PULL 04/47] target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL, Peter Maydell, 2020/09/01
- [PULL 06/47] target/arm: Implement VFP fp16 for fused-multiply-add, Peter Maydell, 2020/09/01
- [PULL 08/47] target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT, Peter Maydell, 2020/09/01
- [PULL 07/47] target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp(), Peter Maydell, 2020/09/01
- [PULL 09/47] target/arm: Implement VFP fp16 for VMOV immediate, Peter Maydell, 2020/09/01
- [PULL 10/47] target/arm: Implement VFP fp16 VCMP, Peter Maydell, 2020/09/01
- [PULL 12/47] target/arm: Implement VFP fp16 VCVT between float and integer, Peter Maydell, 2020/09/01
- [PULL 11/47] target/arm: Implement VFP fp16 VLDR and VSTR, Peter Maydell, 2020/09/01