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[PULL 17/47] target/arm: Implement VFP fp16 VSEL
From: |
Peter Maydell |
Subject: |
[PULL 17/47] target/arm: Implement VFP fp16 VSEL |
Date: |
Tue, 1 Sep 2020 16:17:53 +0100 |
Implement the fp16 versions of the VFP VSEL instruction.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-18-peter.maydell@linaro.org
---
target/arm/vfp-uncond.decode | 6 ++++--
target/arm/translate-vfp.c.inc | 16 ++++++++++++----
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode
index b7cd9d11ed5..8ba7b1703e0 100644
--- a/target/arm/vfp-uncond.decode
+++ b/target/arm/vfp-uncond.decode
@@ -44,10 +44,12 @@
@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VSEL 1111 1110 0. cc:2 .... .... 1001 .0.0 .... \
+ vm=%vm_sp vn=%vn_sp vd=%vd_sp sz=1
VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
+ vm=%vm_sp vn=%vn_sp vd=%vd_sp sz=2
VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp sz=3
VMAXNM_hp 1111 1110 1.00 .... .... 1001 .0.0 .... @vfp_dnm_s
VMINNM_hp 1111 1110 1.00 .... .... 1001 .1.0 .... @vfp_dnm_s
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 583e7ccdb20..869b67b2b93 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -190,18 +190,22 @@ static bool vfp_access_check(DisasContext *s)
static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
{
uint32_t rd, rn, rm;
- bool dp = a->dp;
+ int sz = a->sz;
if (!dc_isar_feature(aa32_vsel, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ if (sz == 3 && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ if (sz == 1 && !dc_isar_feature(aa32_fp16_arith, s)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
+ if (sz == 3 && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
@@ -214,7 +218,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return true;
}
- if (dp) {
+ if (sz == 3) {
TCGv_i64 frn, frm, dest;
TCGv_i64 tmp, zero, zf, nf, vf;
@@ -307,6 +311,10 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
tcg_temp_free_i32(tmp);
break;
}
+ /* For fp16 the top half is always zeroes */
+ if (sz == 1) {
+ tcg_gen_andi_i32(dest, dest, 0xffff);
+ }
neon_store_reg32(dest, rd);
tcg_temp_free_i32(frn);
tcg_temp_free_i32(frm);
--
2.20.1
- [PULL 06/47] target/arm: Implement VFP fp16 for fused-multiply-add, (continued)
- [PULL 06/47] target/arm: Implement VFP fp16 for fused-multiply-add, Peter Maydell, 2020/09/01
- [PULL 08/47] target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT, Peter Maydell, 2020/09/01
- [PULL 07/47] target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp(), Peter Maydell, 2020/09/01
- [PULL 09/47] target/arm: Implement VFP fp16 for VMOV immediate, Peter Maydell, 2020/09/01
- [PULL 10/47] target/arm: Implement VFP fp16 VCMP, Peter Maydell, 2020/09/01
- [PULL 12/47] target/arm: Implement VFP fp16 VCVT between float and integer, Peter Maydell, 2020/09/01
- [PULL 11/47] target/arm: Implement VFP fp16 VLDR and VSTR, Peter Maydell, 2020/09/01
- [PULL 13/47] target/arm: Make VFP_CONV_FIX macros take separate float type and float size, Peter Maydell, 2020/09/01
- [PULL 15/47] target/arm: Implement VFP fp16 VCVT between float and fixed-point, Peter Maydell, 2020/09/01
- [PULL 14/47] target/arm: Use macros instead of open-coding fp16 conversion helpers, Peter Maydell, 2020/09/01
- [PULL 17/47] target/arm: Implement VFP fp16 VSEL,
Peter Maydell <=
- [PULL 19/47] target/arm: Implement new VFP fp16 insn VINS, Peter Maydell, 2020/09/01
- [PULL 20/47] target/arm: Implement new VFP fp16 insn VMOVX, Peter Maydell, 2020/09/01
- [PULL 16/47] target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode, Peter Maydell, 2020/09/01
- [PULL 22/47] target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL, Peter Maydell, 2020/09/01
- [PULL 21/47] target/arm: Implement VFP fp16 VMOV between gp and halfprec registers, Peter Maydell, 2020/09/01
- [PULL 18/47] target/arm: Implement VFP fp16 VRINT*, Peter Maydell, 2020/09/01
- [PULL 23/47] target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec, Peter Maydell, 2020/09/01
- [PULL 24/47] target/arm: Implement fp16 for Neon VABS, VNEG of floats, Peter Maydell, 2020/09/01
- [PULL 25/47] target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons, Peter Maydell, 2020/09/01
- [PULL 27/47] target/arm: Implement fp16 for Neon VMAX, VMIN, Peter Maydell, 2020/09/01