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[PULL 24/47] target/arm: Implement fp16 for Neon VABS, VNEG of floats
From: |
Peter Maydell |
Subject: |
[PULL 24/47] target/arm: Implement fp16 for Neon VABS, VNEG of floats |
Date: |
Tue, 1 Sep 2020 16:18:00 +0100 |
Rewrite Neon VABS/VNEG of floats to use gvec logical AND and XOR, so
that we can implement the fp16 version of the insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-26-peter.maydell@linaro.org
---
target/arm/translate-neon.c.inc | 34 +++++++++++++++++++++++++++------
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index 0a96245e962..45cea6ca766 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -3741,22 +3741,44 @@ static bool trans_VCNT(DisasContext *s, arg_2misc *a)
return do_2misc(s, a, gen_helper_neon_cnt_u8);
}
+static void gen_VABS_F(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ tcg_gen_gvec_andi(vece, rd_ofs, rm_ofs,
+ vece == MO_16 ? 0x7fff : 0x7fffffff,
+ oprsz, maxsz);
+}
+
static bool trans_VABS_F(DisasContext *s, arg_2misc *a)
{
- if (a->size != 2) {
+ if (a->size == MO_16) {
+ if (!dc_isar_feature(aa32_fp16_arith, s)) {
+ return false;
+ }
+ } else if (a->size != MO_32) {
return false;
}
- /* TODO: FP16 : size == 1 */
- return do_2misc(s, a, gen_helper_vfp_abss);
+ return do_2misc_vec(s, a, gen_VABS_F);
+}
+
+static void gen_VNEG_F(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ tcg_gen_gvec_xori(vece, rd_ofs, rm_ofs,
+ vece == MO_16 ? 0x8000 : 0x80000000,
+ oprsz, maxsz);
}
static bool trans_VNEG_F(DisasContext *s, arg_2misc *a)
{
- if (a->size != 2) {
+ if (a->size == MO_16) {
+ if (!dc_isar_feature(aa32_fp16_arith, s)) {
+ return false;
+ }
+ } else if (a->size != MO_32) {
return false;
}
- /* TODO: FP16 : size == 1 */
- return do_2misc(s, a, gen_helper_vfp_negs);
+ return do_2misc_vec(s, a, gen_VNEG_F);
}
static bool trans_VRECPE(DisasContext *s, arg_2misc *a)
--
2.20.1
- [PULL 15/47] target/arm: Implement VFP fp16 VCVT between float and fixed-point, (continued)
- [PULL 15/47] target/arm: Implement VFP fp16 VCVT between float and fixed-point, Peter Maydell, 2020/09/01
- [PULL 14/47] target/arm: Use macros instead of open-coding fp16 conversion helpers, Peter Maydell, 2020/09/01
- [PULL 17/47] target/arm: Implement VFP fp16 VSEL, Peter Maydell, 2020/09/01
- [PULL 19/47] target/arm: Implement new VFP fp16 insn VINS, Peter Maydell, 2020/09/01
- [PULL 20/47] target/arm: Implement new VFP fp16 insn VMOVX, Peter Maydell, 2020/09/01
- [PULL 16/47] target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode, Peter Maydell, 2020/09/01
- [PULL 22/47] target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL, Peter Maydell, 2020/09/01
- [PULL 21/47] target/arm: Implement VFP fp16 VMOV between gp and halfprec registers, Peter Maydell, 2020/09/01
- [PULL 18/47] target/arm: Implement VFP fp16 VRINT*, Peter Maydell, 2020/09/01
- [PULL 23/47] target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec, Peter Maydell, 2020/09/01
- [PULL 24/47] target/arm: Implement fp16 for Neon VABS, VNEG of floats,
Peter Maydell <=
- [PULL 25/47] target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons, Peter Maydell, 2020/09/01
- [PULL 27/47] target/arm: Implement fp16 for Neon VMAX, VMIN, Peter Maydell, 2020/09/01
- [PULL 28/47] target/arm: Implement fp16 for Neon VMAXNM, VMINNM, Peter Maydell, 2020/09/01
- [PULL 29/47] target/arm: Implement fp16 for Neon VMLA, VMLS operations, Peter Maydell, 2020/09/01
- [PULL 30/47] target/arm: Implement fp16 for Neon VFMA, VMFS, Peter Maydell, 2020/09/01
- [PULL 26/47] target/arm: Implement fp16 for VACGE, VACGT, Peter Maydell, 2020/09/01
- [PULL 31/47] target/arm: Implement fp16 for Neon fp compare-vs-0, Peter Maydell, 2020/09/01
- [PULL 33/47] target/arm: Implement fp16 for Neon VRSQRTS, Peter Maydell, 2020/09/01
- [PULL 34/47] target/arm: Implement fp16 for Neon pairwise fp ops, Peter Maydell, 2020/09/01
- [PULL 35/47] target/arm: Implement fp16 for Neon float-integer VCVT, Peter Maydell, 2020/09/01