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[PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc
From: |
Bin Meng |
Subject: |
[PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc |
Date: |
Thu, 3 Sep 2020 18:40:12 +0800 |
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_e_prci model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
include/hw/{riscv => misc}/sifive_e_prci.h | 0
hw/{riscv => misc}/sifive_e_prci.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/misc/Kconfig | 3 +++
hw/misc/meson.build | 3 +++
hw/riscv/Kconfig | 1 +
hw/riscv/meson.build | 1 -
7 files changed, 9 insertions(+), 3 deletions(-)
rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
rename hw/{riscv => misc}/sifive_e_prci.c (99%)
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
similarity index 100%
rename from include/hw/riscv/sifive_e_prci.h
rename to include/hw/misc/sifive_e_prci.h
diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
similarity index 99%
rename from hw/riscv/sifive_e_prci.c
rename to hw/misc/sifive_e_prci.c
index 17dfa74..8ec4ee4 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/misc/sifive_e_prci.c
@@ -24,7 +24,7 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/hw.h"
-#include "hw/riscv/sifive_e_prci.h"
+#include "hw/misc/sifive_e_prci.h"
static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int
size)
{
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 36ccfb2..7f43ed9 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -43,8 +43,8 @@
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h"
-#include "hw/riscv/sifive_e_prci.h"
#include "hw/riscv/boot.h"
+#include "hw/misc/sifive_e_prci.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/sysemu.h"
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 92c397c..5073986 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -134,4 +134,7 @@ config MAC_VIA
config AVR_POWER
bool
+config SIFIVE_E_PRCI
+ bool
+
source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index e1576b8..b6b2e57 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -21,6 +21,9 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true:
files('arm11scu.c'))
# Mac devices
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
+# RISC-V devices
+softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+
# PKUnity SoC devices
softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index e53ab1e..5855e99 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -15,6 +15,7 @@ config SIFIVE_E
bool
select HART
select SIFIVE
+ select SIFIVE_E_PRCI
select UNIMP
config SIFIVE_U
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index cf1aa99..d73ea99 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -10,7 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true:
files('sifive_plic.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
--
2.7.4
- [PATCH 00/12] hw/riscv: Clean up the directory, Bin Meng, 2020/09/03
- [PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc,
Bin Meng <=
- [PATCH 02/12] hw/riscv: Move sifive_u_prci model to hw/misc, Bin Meng, 2020/09/03
- [PATCH 03/12] hw/riscv: Move sifive_u_otp model to hw/misc, Bin Meng, 2020/09/03
- [PATCH 04/12] hw/riscv: Move sifive_gpio model to hw/gpio, Bin Meng, 2020/09/03
- [PATCH 06/12] hw/riscv: Move sifive_plic model to hw/intc, Bin Meng, 2020/09/03
- [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc, Bin Meng, 2020/09/03