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Re: [PATCH 02/12] hw/riscv: Move sifive_u_prci model to hw/misc
From: |
Alistair Francis |
Subject: |
Re: [PATCH 02/12] hw/riscv: Move sifive_u_prci model to hw/misc |
Date: |
Fri, 4 Sep 2020 10:25:50 -0700 |
On Thu, Sep 3, 2020 at 3:41 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_u_prci model to hw/misc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> include/hw/{riscv => misc}/sifive_u_prci.h | 0
> include/hw/riscv/sifive_u.h | 2 +-
> hw/{riscv => misc}/sifive_u_prci.c | 2 +-
> hw/misc/Kconfig | 3 +++
> hw/misc/meson.build | 1 +
> hw/riscv/Kconfig | 1 +
> hw/riscv/meson.build | 1 -
> 7 files changed, 7 insertions(+), 3 deletions(-)
> rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
> rename hw/{riscv => misc}/sifive_u_prci.c (99%)
>
> diff --git a/include/hw/riscv/sifive_u_prci.h
> b/include/hw/misc/sifive_u_prci.h
> similarity index 100%
> rename from include/hw/riscv/sifive_u_prci.h
> rename to include/hw/misc/sifive_u_prci.h
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 793000a..cbeb228 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -24,8 +24,8 @@
> #include "hw/riscv/riscv_hart.h"
> #include "hw/riscv/sifive_cpu.h"
> #include "hw/riscv/sifive_gpio.h"
> -#include "hw/riscv/sifive_u_prci.h"
> #include "hw/riscv/sifive_u_otp.h"
> +#include "hw/misc/sifive_u_prci.h"
>
> #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
> #define RISCV_U_SOC(obj) \
> diff --git a/hw/riscv/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
> similarity index 99%
> rename from hw/riscv/sifive_u_prci.c
> rename to hw/misc/sifive_u_prci.c
> index 4fa590c..5d9d446 100644
> --- a/hw/riscv/sifive_u_prci.c
> +++ b/hw/misc/sifive_u_prci.c
> @@ -22,7 +22,7 @@
> #include "hw/sysbus.h"
> #include "qemu/log.h"
> #include "qemu/module.h"
> -#include "hw/riscv/sifive_u_prci.h"
> +#include "hw/misc/sifive_u_prci.h"
>
> static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int
> size)
> {
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 5073986..65f3fdd 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -137,4 +137,7 @@ config AVR_POWER
> config SIFIVE_E_PRCI
> bool
>
> +config SIFIVE_U_PRCI
> + bool
> +
> source macio/Kconfig
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index b6b2e57..9e9550e 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true:
> files('mos6522.c'))
>
> # RISC-V devices
> softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true:
> files('sifive_e_prci.c'))
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true:
> files('sifive_u_prci.c'))
>
> # PKUnity SoC devices
> softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 5855e99..109364b 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -24,6 +24,7 @@ config SIFIVE_U
> select HART
> select SIFIVE
> select SIFIVE_PDMA
> + select SIFIVE_U_PRCI
> select UNIMP
>
> config SPIKE
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index d73ea99..e6c8af0 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -12,7 +12,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true:
> files('sifive_uart.c'))
> riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
> riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
> riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
> riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
> riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
> riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true:
> files('microchip_pfsoc.c'))
> --
> 2.7.4
>
>
- [PATCH 00/12] hw/riscv: Clean up the directory, Bin Meng, 2020/09/03
- [PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc, Bin Meng, 2020/09/03
- [PATCH 02/12] hw/riscv: Move sifive_u_prci model to hw/misc, Bin Meng, 2020/09/03
- Re: [PATCH 02/12] hw/riscv: Move sifive_u_prci model to hw/misc,
Alistair Francis <=
- [PATCH 03/12] hw/riscv: Move sifive_u_otp model to hw/misc, Bin Meng, 2020/09/03
- [PATCH 04/12] hw/riscv: Move sifive_gpio model to hw/gpio, Bin Meng, 2020/09/03
- [PATCH 06/12] hw/riscv: Move sifive_plic model to hw/intc, Bin Meng, 2020/09/03
- [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc, Bin Meng, 2020/09/03
- [PATCH 07/12] hw/riscv: Move riscv_htif model to hw/char, Bin Meng, 2020/09/03