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[PULL 01/30] target/riscv: Fix bug in getting trap cause name for trace_
From: |
Alistair Francis |
Subject: |
[PULL 01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap |
Date: |
Thu, 10 Sep 2020 11:09:09 -0700 |
From: Yifei Jiang <jiangyifei@huawei.com>
When the cause number is equal to or greater than 23, print "(unknown)" in
trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last
excpetion "guest_store_page_fault" can not be printed.
In addition, the current check of cause is invalid for riscv_intr_names. So
introduce riscv_cpu_get_trap_name to get the trap cause name.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 11 +++++++++++
target/riscv/cpu_helper.c | 4 ++--
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 383808bf88..d3589ae6ea 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -312,6 +312,7 @@ extern const char * const riscv_fpr_regnames[];
extern const char * const riscv_excp_names[];
extern const char * const riscv_intr_names[];
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 228b9bdb5d..bcdce85c5e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -96,6 +96,17 @@ const char * const riscv_intr_names[] = {
"reserved"
};
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
+{
+ if (async) {
+ return (cause < ARRAY_SIZE(riscv_intr_names)) ?
+ riscv_intr_names[cause] : "(unknown)";
+ } else {
+ return (cause < ARRAY_SIZE(riscv_excp_names)) ?
+ riscv_excp_names[cause] : "(unknown)";
+ }
+}
+
static void set_misa(CPURISCVState *env, target_ulong misa)
{
env->misa_mask = env->misa = misa;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index dc7ae3e7b1..005880627e 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -892,8 +892,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
}
- trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ?
- (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
+ trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
+ riscv_cpu_get_trap_name(cause, async));
if (env->priv <= PRV_S &&
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
--
2.28.0
- [PULL 00/30] riscv-to-apply queue, Alistair Francis, 2020/09/10
- [PULL 00/30] riscv-to-apply queue, Alistair Francis, 2020/09/10
- [PULL 02/30] riscv: sifive_test: Allow 16-bit writes to memory region, Alistair Francis, 2020/09/10
- [PULL 01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap,
Alistair Francis <=
- [PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property, Alistair Francis, 2020/09/10
- [PULL 05/30] target/riscv: cpu: Set reset vector based on the configured property value, Alistair Francis, 2020/09/10
- [PULL 04/30] hw/riscv: hart: Add a new 'resetvec' property, Alistair Francis, 2020/09/10
- [PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation, Alistair Francis, 2020/09/10
- [PULL 08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs, Alistair Francis, 2020/09/10
- [PULL 09/30] hw/sd: Add Cadence SDHCI emulation, Alistair Francis, 2020/09/10
- [PULL 06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board, Alistair Francis, 2020/09/10
- [PULL 11/30] hw/dma: Add SiFive platform DMA controller emulation, Alistair Francis, 2020/09/10
- [PULL 10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card, Alistair Francis, 2020/09/10
- [PULL 12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller, Alistair Francis, 2020/09/10