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[PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property
From: |
Alistair Francis |
Subject: |
[PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property |
Date: |
Thu, 10 Sep 2020 11:09:11 -0700 |
From: Bin Meng <bin.meng@windriver.com>
Currently the reset vector address is hard-coded in a RISC-V CPU's
instance_init() routine. In a real world we can have 2 exact same
CPUs except for the reset vector address, which is pretty common in
the RISC-V core IP licensing business.
Normally reset vector address is a configurable parameter. Let's
create a 64-bit property to store the reset vector address which
covers both 32-bit and 64-bit CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d3589ae6ea..0d1728a8cd 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -291,6 +291,7 @@ typedef struct RISCVCPU {
uint16_t elen;
bool mmu;
bool pmp;
+ uint64_t resetvec;
} cfg;
} RISCVCPU;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bcdce85c5e..f6aeecac15 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -529,6 +529,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
DEFINE_PROP_END_OF_LIST(),
};
--
2.28.0
- [PULL 00/30] riscv-to-apply queue, Alistair Francis, 2020/09/10
- [PULL 00/30] riscv-to-apply queue, Alistair Francis, 2020/09/10
- [PULL 02/30] riscv: sifive_test: Allow 16-bit writes to memory region, Alistair Francis, 2020/09/10
- [PULL 01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap, Alistair Francis, 2020/09/10
- [PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property,
Alistair Francis <=
- [PULL 05/30] target/riscv: cpu: Set reset vector based on the configured property value, Alistair Francis, 2020/09/10
- [PULL 04/30] hw/riscv: hart: Add a new 'resetvec' property, Alistair Francis, 2020/09/10
- [PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation, Alistair Francis, 2020/09/10
- [PULL 08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs, Alistair Francis, 2020/09/10
- [PULL 09/30] hw/sd: Add Cadence SDHCI emulation, Alistair Francis, 2020/09/10
- [PULL 06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board, Alistair Francis, 2020/09/10
- [PULL 11/30] hw/dma: Add SiFive platform DMA controller emulation, Alistair Francis, 2020/09/10
- [PULL 10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card, Alistair Francis, 2020/09/10
- [PULL 12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller, Alistair Francis, 2020/09/10
- [PULL 13/30] hw/net: cadence_gem: Add a new 'phy-addr' property, Alistair Francis, 2020/09/10