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[PULL 24/30] hw/riscv: Move sifive_plic model to hw/intc
From: |
Alistair Francis |
Subject: |
[PULL 24/30] hw/riscv: Move sifive_plic model to hw/intc |
Date: |
Thu, 10 Sep 2020 11:09:32 -0700 |
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
{include/hw/riscv => hw/intc}/sifive_plic.h | 0
hw/{riscv => intc}/sifive_plic.c | 2 +-
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/virt.c | 2 +-
hw/intc/Kconfig | 3 +++
hw/intc/meson.build | 1 +
hw/riscv/Kconfig | 5 +++++
hw/riscv/meson.build | 1 -
10 files changed, 14 insertions(+), 6 deletions(-)
rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
rename hw/{riscv => intc}/sifive_plic.c (99%)
diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
similarity index 100%
rename from include/hw/riscv/sifive_plic.h
rename to hw/intc/sifive_plic.h
diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
similarity index 99%
rename from hw/riscv/sifive_plic.c
rename to hw/intc/sifive_plic.c
index 11ef147606..af611f8db8 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -27,9 +27,9 @@
#include "hw/pci/msi.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
+#include "hw/intc/sifive_plic.h"
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
-#include "hw/riscv/sifive_plic.h"
#define RISCV_DEBUG_PLIC 0
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 131eea1ef3..4627179cd3 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -48,9 +48,9 @@
#include "hw/misc/unimp.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/microchip_pfsoc.h"
#include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
#include "sysemu/sysemu.h"
/*
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 3bdb16e697..0ddcf1508d 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -39,11 +39,11 @@
#include "hw/misc/unimp.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h"
#include "hw/riscv/boot.h"
#include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_e_prci.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7187d1ad17..faca2e829e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -46,11 +46,11 @@
#include "hw/misc/unimp.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
#include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
#include "chardev/char.h"
#include "net/eth.h"
#include "sysemu/arch_init.h"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index bce2020d02..0caab8e050 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -30,12 +30,12 @@
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_test.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/numa.h"
#include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index f499d0f8df..d07954086a 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -70,3 +70,6 @@ config LOONGSON_LIOINTC
config SIFIVE_CLINT
bool
+
+config SIFIVE_PLIC
+ bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 1e20daab77..3f82cc230a 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -48,6 +48,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true:
files('s390_flic.c'))
specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true:
files('s390_flic_kvm.c'))
specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
+specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index f8bb7e7a05..23b7027e11 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -17,6 +17,7 @@ config SIFIVE_E
select SIFIVE
select SIFIVE_CLINT
select SIFIVE_GPIO
+ select SIFIVE_PLIC
select SIFIVE_E_PRCI
select UNIMP
@@ -28,6 +29,7 @@ config SIFIVE_U
select SIFIVE_CLINT
select SIFIVE_GPIO
select SIFIVE_PDMA
+ select SIFIVE_PLIC
select SIFIVE_U_OTP
select SIFIVE_U_PRCI
select UNIMP
@@ -38,6 +40,7 @@ config SPIKE
select HTIF
select SIFIVE
select SIFIVE_CLINT
+ select SIFIVE_PLIC
config OPENTITAN
bool
@@ -58,6 +61,7 @@ config RISCV_VIRT
select PFLASH_CFI01
select SIFIVE
select SIFIVE_CLINT
+ select SIFIVE_PLIC
config MICROCHIP_PFSOC
bool
@@ -67,4 +71,5 @@ config MICROCHIP_PFSOC
select UNIMP
select MCHP_PFSOC_MMUART
select SIFIVE_PDMA
+ select SIFIVE_PLIC
select CADENCE_SDHCI
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index d0b4cafaec..df3f89d062 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
--
2.28.0
- [PULL 15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs, (continued)
- [PULL 15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs, Alistair Francis, 2020/09/10
- [PULL 16/30] hw/riscv: microchip_pfsoc: Hook GPIO controllers, Alistair Francis, 2020/09/10
- [PULL 18/30] hw/riscv: sifive_u: Connect a DMA controller, Alistair Francis, 2020/09/10
- [PULL 17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency, Alistair Francis, 2020/09/10
- [PULL 19/30] hw/riscv: Move sifive_e_prci model to hw/misc, Alistair Francis, 2020/09/10
- [PULL 20/30] hw/riscv: Move sifive_u_prci model to hw/misc, Alistair Francis, 2020/09/10
- [PULL 21/30] hw/riscv: Move sifive_u_otp model to hw/misc, Alistair Francis, 2020/09/10
- [PULL 22/30] hw/riscv: Move sifive_gpio model to hw/gpio, Alistair Francis, 2020/09/10
- [PULL 25/30] hw/riscv: Move riscv_htif model to hw/char, Alistair Francis, 2020/09/10
- [PULL 23/30] hw/riscv: Move sifive_clint model to hw/intc, Alistair Francis, 2020/09/10
- [PULL 24/30] hw/riscv: Move sifive_plic model to hw/intc,
Alistair Francis <=
- [PULL 27/30] hw/riscv: Move sifive_test model to hw/misc, Alistair Francis, 2020/09/10
- [PULL 28/30] hw/riscv: Always build riscv_hart.c, Alistair Francis, 2020/09/10
- [PULL 29/30] hw/riscv: Drop CONFIG_SIFIVE, Alistair Francis, 2020/09/10
- [PULL 26/30] hw/riscv: Move sifive_uart model to hw/char, Alistair Francis, 2020/09/10
- [PULL 30/30] hw/riscv: Sort the Kconfig options in alphabetical order, Alistair Francis, 2020/09/10
- Re: [PULL 00/30] riscv-to-apply queue, Peter Maydell, 2020/09/13