[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 26/30] hw/riscv: Move sifive_uart model to hw/char
From: |
Alistair Francis |
Subject: |
[PULL 26/30] hw/riscv: Move sifive_uart model to hw/char |
Date: |
Thu, 10 Sep 2020 11:09:34 -0700 |
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/{riscv => char}/sifive_uart.h | 0
hw/{riscv => char}/sifive_uart.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/char/Kconfig | 3 +++
hw/char/meson.build | 1 +
hw/riscv/Kconfig | 2 ++
hw/riscv/meson.build | 1 -
8 files changed, 9 insertions(+), 4 deletions(-)
rename include/hw/{riscv => char}/sifive_uart.h (100%)
rename hw/{riscv => char}/sifive_uart.c (99%)
diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h
similarity index 100%
rename from include/hw/riscv/sifive_uart.h
rename to include/hw/char/sifive_uart.h
diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c
similarity index 99%
rename from hw/riscv/sifive_uart.c
rename to hw/char/sifive_uart.c
index 9350482662..3a00ba7f00 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -24,7 +24,7 @@
#include "chardev/char-fe.h"
#include "hw/hw.h"
#include "hw/irq.h"
-#include "hw/riscv/sifive_uart.h"
+#include "hw/char/sifive_uart.h"
/*
* Not yet implemented:
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 0ddcf1508d..40bbf530d4 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -39,9 +39,9 @@
#include "hw/misc/unimp.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h"
#include "hw/riscv/boot.h"
+#include "hw/char/sifive_uart.h"
#include "hw/intc/sifive_clint.h"
#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_e_prci.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index faca2e829e..4f12a93188 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -46,9 +46,9 @@
#include "hw/misc/unimp.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
+#include "hw/char/sifive_uart.h"
#include "hw/intc/sifive_clint.h"
#include "hw/intc/sifive_plic.h"
#include "chardev/char.h"
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index 91da92f617..939bc44758 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -58,3 +58,6 @@ config AVR_USART
config MCHP_PFSOC_MMUART
bool
+
+config SIFIVE_UART
+ bool
diff --git a/hw/char/meson.build b/hw/char/meson.build
index 3db623eeec..196ac91fa2 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -30,6 +30,7 @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true:
files('exynos4210_uart.c'))
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true:
files('stm32f2xx_usart.c'))
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true:
files('mchp_pfsoc_mmuart.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index a0e256c344..a0461578a6 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -15,6 +15,7 @@ config SIFIVE_E
select SIFIVE_CLINT
select SIFIVE_GPIO
select SIFIVE_PLIC
+ select SIFIVE_UART
select SIFIVE_E_PRCI
select UNIMP
@@ -27,6 +28,7 @@ config SIFIVE_U
select SIFIVE_GPIO
select SIFIVE_PDMA
select SIFIVE_PLIC
+ select SIFIVE_UART
select SIFIVE_U_OTP
select SIFIVE_U_PRCI
select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 90df67acc7..967572d4f6 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true:
files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
--
2.28.0
- [PULL 19/30] hw/riscv: Move sifive_e_prci model to hw/misc, (continued)
- [PULL 19/30] hw/riscv: Move sifive_e_prci model to hw/misc, Alistair Francis, 2020/09/10
- [PULL 20/30] hw/riscv: Move sifive_u_prci model to hw/misc, Alistair Francis, 2020/09/10
- [PULL 21/30] hw/riscv: Move sifive_u_otp model to hw/misc, Alistair Francis, 2020/09/10
- [PULL 22/30] hw/riscv: Move sifive_gpio model to hw/gpio, Alistair Francis, 2020/09/10
- [PULL 25/30] hw/riscv: Move riscv_htif model to hw/char, Alistair Francis, 2020/09/10
- [PULL 23/30] hw/riscv: Move sifive_clint model to hw/intc, Alistair Francis, 2020/09/10
- [PULL 24/30] hw/riscv: Move sifive_plic model to hw/intc, Alistair Francis, 2020/09/10
- [PULL 27/30] hw/riscv: Move sifive_test model to hw/misc, Alistair Francis, 2020/09/10
- [PULL 28/30] hw/riscv: Always build riscv_hart.c, Alistair Francis, 2020/09/10
- [PULL 29/30] hw/riscv: Drop CONFIG_SIFIVE, Alistair Francis, 2020/09/10
- [PULL 26/30] hw/riscv: Move sifive_uart model to hw/char,
Alistair Francis <=
- [PULL 30/30] hw/riscv: Sort the Kconfig options in alphabetical order, Alistair Francis, 2020/09/10
- Re: [PULL 00/30] riscv-to-apply queue, Peter Maydell, 2020/09/13