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[RFC PATCH v4 05/29] Hexagon (disas) disassembler
From: |
Taylor Simpson |
Subject: |
[RFC PATCH v4 05/29] Hexagon (disas) disassembler |
Date: |
Mon, 28 Sep 2020 12:28:34 -0500 |
Add hexagon to disas/meson.build
Add disas/hexagon.c
Add hexagon to include/disas/dis-asm.h
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
include/disas/dis-asm.h | 1 +
disas/hexagon.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++++
disas/meson.build | 1 +
3 files changed, 64 insertions(+)
create mode 100644 disas/hexagon.c
diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
index 9856bf7..14ff2be 100644
--- a/include/disas/dis-asm.h
+++ b/include/disas/dis-asm.h
@@ -460,6 +460,7 @@ int print_insn_xtensa (bfd_vma,
disassemble_info*);
int print_insn_riscv32 (bfd_vma, disassemble_info*);
int print_insn_riscv64 (bfd_vma, disassemble_info*);
int print_insn_rx(bfd_vma, disassemble_info *);
+int print_insn_hexagon(bfd_vma, disassemble_info *);
#if 0
/* Fetch the disassembler for a given BFD, if that support is available. */
diff --git a/disas/hexagon.c b/disas/hexagon.c
new file mode 100644
index 0000000..6ee8653
--- /dev/null
+++ b/disas/hexagon.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * QEMU Hexagon Disassembler
+ */
+
+#include "qemu/osdep.h"
+#include "disas/dis-asm.h"
+#include "target/hexagon/cpu_bits.h"
+
+/*
+ * We will disassemble a packet with up to 4 instructions, so we need
+ * a hefty size buffer.
+ */
+#define PACKET_BUFFER_LEN 1028
+
+int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)
+{
+ uint32_t words[PACKET_WORDS_MAX];
+ int len, slen;
+ char buf[PACKET_BUFFER_LEN];
+ int status;
+ int i;
+
+ for (i = 0; i < PACKET_WORDS_MAX; i++) {
+ status = (*info->read_memory_func)(memaddr + i * sizeof(uint32_t),
+ (bfd_byte *)&words[i],
+ sizeof(uint32_t), info);
+ if (status) {
+ if (i > 0) {
+ break;
+ }
+ (*info->memory_error_func)(status, memaddr, info);
+ return status;
+ }
+ }
+
+ len = disassemble_hexagon(words, i, buf, PACKET_BUFFER_LEN);
+ slen = strlen(buf);
+ if (buf[slen - 1] == '\n') {
+ buf[slen - 1] = '\0';
+ }
+ (*info->fprintf_func)(info->stream, "%s", buf);
+
+ return len;
+}
+
diff --git a/disas/meson.build b/disas/meson.build
index bde8280..4468d10 100644
--- a/disas/meson.build
+++ b/disas/meson.build
@@ -7,6 +7,7 @@ common_ss.add_all(when: 'CONFIG_ARM_A64_DIS', if_true:
libvixl_ss)
common_ss.add(when: 'CONFIG_ARM_DIS', if_true: files('arm.c'))
common_ss.add(when: 'CONFIG_CRIS_DIS', if_true: files('cris.c'))
common_ss.add(when: 'CONFIG_HPPA_DIS', if_true: files('hppa.c'))
+common_ss.add(when: 'CONFIG_HEXAGON_DIS', if_true: files('hexagon.c'))
common_ss.add(when: 'CONFIG_I386_DIS', if_true: files('i386.c'))
common_ss.add(when: 'CONFIG_LM32_DIS', if_true: files('lm32.c'))
common_ss.add(when: 'CONFIG_M68K_DIS', if_true: files('m68k.c'))
--
2.7.4
- [RFC PATCH v4 00/29] Hexagon patch series, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 01/29] Hexagon Update MAINTAINERS file, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 03/29] Hexagon (include/elf.h) ELF machine definition, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 02/29] Hexagon (target/hexagon) README, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 04/29] Hexagon (target/hexagon) scalar core definition, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 13/29] Hexagon (target/hexagon) instruction/packet decode, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 11/29] Hexagon (target/hexagon) register fields, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 06/29] Hexagon (target/hexagon) register names, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 08/29] Hexagon (target/hexagon) GDB Stub, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 05/29] Hexagon (disas) disassembler,
Taylor Simpson <=
- [RFC PATCH v4 07/29] Hexagon (target/hexagon) scalar core helpers, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 10/29] Hexagon (target/hexagon) instruction and packet types, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 19/29] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 12/29] Hexagon (target/hexagon) instruction attributes, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 09/29] Hexagon (target/hexagon) architecture types, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 17/29] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 20/29] Hexagon (target/hexagon) generater phase 4 - decode tree, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 14/29] Hexagon (target/hexagon) instruction printing, Taylor Simpson, 2020/09/28