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[RFC PATCH v4 10/29] Hexagon (target/hexagon) instruction and packet typ
From: |
Taylor Simpson |
Subject: |
[RFC PATCH v4 10/29] Hexagon (target/hexagon) instruction and packet types |
Date: |
Mon, 28 Sep 2020 12:28:39 -0500 |
The insn_t and packet_t are the interface between instruction decoding and
TCG code generation
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/insn.h | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
create mode 100644 target/hexagon/insn.h
diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h
new file mode 100644
index 0000000..087cc6e
--- /dev/null
+++ b/target/hexagon/insn.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HEXAGON_INSN_H
+#define HEXAGON_INSN_H
+
+#include "cpu.h"
+
+#define INSTRUCTIONS_MAX 7 /* 2 pairs + loopend */
+#define REG_OPERANDS_MAX 5
+#define IMMEDS_MAX 2
+
+struct Instruction;
+struct Packet;
+struct DisasContext;
+
+typedef void (*semantic_insn_t)(CPUHexagonState *env,
+ struct DisasContext *ctx,
+ struct Instruction *insn,
+ struct Packet *pkt);
+
+struct Instruction {
+ semantic_insn_t generate; /* pointer to genptr routine */
+ uint8_t regno[REG_OPERANDS_MAX]; /* reg operands including predicates */
+ uint16_t opcode;
+
+ uint32_t iclass:6;
+ uint32_t slot:3;
+ uint32_t part1:1; /*
+ * cmp-jumps are split into two insns.
+ * set for the compare and clear for the jump
+ */
+ uint32_t extension_valid:1; /* Has a constant extender attached */
+ uint32_t which_extended:1; /* If has an extender, which immediate */
+ uint32_t is_endloop:1; /* This is an end of loop */
+ uint32_t new_value_producer_slot:4;
+ int32_t immed[IMMEDS_MAX]; /* immediate field */
+};
+
+typedef struct Instruction insn_t;
+
+struct Packet {
+ uint16_t num_insns;
+ uint16_t encod_pkt_size_in_bytes;
+
+ /* Pre-decodes about COF */
+ uint32_t pkt_has_cof:1; /* Has any change-of-flow */
+ uint32_t pkt_has_endloop:1;
+
+ uint32_t pkt_has_dczeroa:1;
+
+ uint32_t pkt_has_store_s0:1;
+ uint32_t pkt_has_store_s1:1;
+
+ insn_t insn[INSTRUCTIONS_MAX];
+};
+
+typedef struct Packet packet_t;
+
+#endif
--
2.7.4
- [RFC PATCH v4 01/29] Hexagon Update MAINTAINERS file, (continued)
- [RFC PATCH v4 01/29] Hexagon Update MAINTAINERS file, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 03/29] Hexagon (include/elf.h) ELF machine definition, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 02/29] Hexagon (target/hexagon) README, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 04/29] Hexagon (target/hexagon) scalar core definition, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 13/29] Hexagon (target/hexagon) instruction/packet decode, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 11/29] Hexagon (target/hexagon) register fields, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 06/29] Hexagon (target/hexagon) register names, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 08/29] Hexagon (target/hexagon) GDB Stub, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 05/29] Hexagon (disas) disassembler, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 07/29] Hexagon (target/hexagon) scalar core helpers, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 10/29] Hexagon (target/hexagon) instruction and packet types,
Taylor Simpson <=
- [RFC PATCH v4 19/29] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 12/29] Hexagon (target/hexagon) instruction attributes, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 09/29] Hexagon (target/hexagon) architecture types, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 17/29] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 20/29] Hexagon (target/hexagon) generater phase 4 - decode tree, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 14/29] Hexagon (target/hexagon) instruction printing, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 23/29] Hexagon (target/hexagon) instruction classes, Taylor Simpson, 2020/09/28
- [RFC PATCH v4 22/29] Hexagon (target/hexagon) macros, Taylor Simpson, 2020/09/28