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[RFC v5 09/68] target/riscv: rvv-1.0: add vlenb register
From: |
frank . chang |
Subject: |
[RFC v5 09/68] target/riscv: rvv-1.0: add vlenb register |
Date: |
Wed, 30 Sep 2020 03:03:44 +0800 |
From: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 0cf8a04dd8..1a84b7fd75 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -63,6 +63,7 @@
#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
/* VCSR fields */
#define VCSR_VXSAT_SHIFT 0
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index aa58b0b369..cf9718908e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -241,6 +241,12 @@ static int read_vtype(CPURISCVState *env, int csrno,
target_ulong *val)
return 0;
}
+static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env_archcpu(env)->cfg.vlen >> 3;
+ return 0;
+}
+
static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->vl;
@@ -1400,6 +1406,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VCSR] = { vs, read_vcsr, write_vcsr },
[CSR_VL] = { vs, read_vl },
[CSR_VTYPE] = { vs, read_vtype },
+ [CSR_VLENB] = { vs, read_vlenb },
/* User Timers and Counters */
[CSR_CYCLE] = { ctr, read_instret },
[CSR_INSTRET] = { ctr, read_instret },
--
2.17.1
- [RFC v5 00/68] support vector extension v1.0, frank . chang, 2020/09/29
- [RFC v5 01/68] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2020/09/29
- [RFC v5 02/68] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2020/09/29
- [RFC v5 03/68] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2020/09/29
- [RFC v5 04/68] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2020/09/29
- [RFC v5 05/68] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2020/09/29
- [RFC v5 07/68] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2020/09/29
- [RFC v5 06/68] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2020/09/29
- [RFC v5 08/68] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2020/09/29
- [RFC v5 09/68] target/riscv: rvv-1.0: add vlenb register,
frank . chang <=
- [RFC v5 10/68] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2020/09/29
- [RFC v5 11/68] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2020/09/29
- [RFC v5 12/68] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2020/09/29
- [RFC v5 13/68] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2020/09/29
- [RFC v5 14/68] target/riscv: rvv-1.0: update check functions, frank . chang, 2020/09/29
- [RFC v5 15/68] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2020/09/29
- [RFC v5 16/68] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2020/09/29
- [RFC v5 17/68] target/riscv: rvv-1.0: configure instructions, frank . chang, 2020/09/29
- [RFC v5 18/68] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2020/09/29
- [RFC v5 19/68] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2020/09/29