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[RFC v5 17/68] target/riscv: rvv-1.0: configure instructions
From: |
frank . chang |
Subject: |
[RFC v5 17/68] target/riscv: rvv-1.0: configure instructions |
Date: |
Wed, 30 Sep 2020 03:03:52 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 14 ++++++++++----
target/riscv/vector_helper.c | 14 +++++++++++++-
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5ade7adc83..bf6ae18abf 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -143,8 +143,10 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
s2 = tcg_temp_new();
dst = tcg_temp_new();
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
+ if (a->rd == 0 && a->rs1 == 0) {
+ s1 = tcg_temp_new();
+ tcg_gen_mov_tl(s1, cpu_vl);
+ } else if (a->rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_const_tl(RV_VLEN_MAX);
} else {
@@ -176,8 +178,10 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli
*a)
s2 = tcg_const_tl(a->zimm);
dst = tcg_temp_new();
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
+ if (a->rd == 0 && a->rs1 == 0) {
+ s1 = tcg_temp_new();
+ tcg_gen_mov_tl(s1, cpu_vl);
+ } else if (a->rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_const_tl(RV_VLEN_MAX);
} else {
@@ -187,6 +191,8 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
gen_helper_vsetvl(dst, cpu_env, s1, s2);
gen_set_gpr(a->rd, dst);
mark_vs_dirty(ctx);
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ lookup_and_goto_ptr(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
tcg_temp_free(s1);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 89aa7cbf73..61917d34ff 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -31,12 +31,24 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env,
target_ulong s1,
{
int vlmax, vl;
RISCVCPU *cpu = env_archcpu(env);
+ uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL);
uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
bool vill = FIELD_EX64(s2, VTYPE, VILL);
target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
- if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
+ if (lmul & 4) {
+ /* Fractional LMUL. */
+ if (lmul == 4 ||
+ cpu->cfg.elen >> (8 - lmul) < sew) {
+ vill = true;
+ }
+ }
+
+ if ((sew > cpu->cfg.elen)
+ || vill
+ || (ediv != 0)
+ || (reserved != 0)) {
/* only set vill bit. */
env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
env->vl = 0;
--
2.17.1
- [RFC v5 06/68] target/riscv: rvv-1.0: add translation-time vector context status, (continued)
- [RFC v5 06/68] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2020/09/29
- [RFC v5 08/68] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2020/09/29
- [RFC v5 09/68] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2020/09/29
- [RFC v5 10/68] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2020/09/29
- [RFC v5 11/68] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2020/09/29
- [RFC v5 12/68] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2020/09/29
- [RFC v5 13/68] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2020/09/29
- [RFC v5 14/68] target/riscv: rvv-1.0: update check functions, frank . chang, 2020/09/29
- [RFC v5 15/68] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2020/09/29
- [RFC v5 16/68] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2020/09/29
- [RFC v5 17/68] target/riscv: rvv-1.0: configure instructions,
frank . chang <=
- [RFC v5 18/68] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2020/09/29
- [RFC v5 19/68] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2020/09/29
- [RFC v5 20/68] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/09/29
- [RFC v5 21/68] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2020/09/29
- [RFC v5 22/68] target/riscv: rvv-1.0: amo operations, frank . chang, 2020/09/29
- [RFC v5 23/68] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/09/29
- [RFC v5 24/68] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/09/29
- [RFC v5 25/68] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/09/29
- [RFC v5 26/68] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2020/09/29
- [RFC v5 27/68] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/09/29