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[RFC v5 20/68] target/riscv: rvv-1.0: fix address index overflow bug of
From: |
frank . chang |
Subject: |
[RFC v5 20/68] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns |
Date: |
Wed, 30 Sep 2020 03:03:55 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/vector_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 368259f75a..9349a36b41 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -361,10 +361,10 @@ static target_ulong NAME(target_ulong base, \
return (base + *((ETYPE *)vs2 + H(idx))); \
}
-GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
-GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
-GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
-GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
+GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1)
+GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2)
+GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4)
+GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8)
static inline void
vext_ldst_index(void *vd, void *v0, target_ulong base,
--
2.17.1
- [RFC v5 10/68] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, (continued)
- [RFC v5 10/68] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2020/09/29
- [RFC v5 11/68] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2020/09/29
- [RFC v5 12/68] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2020/09/29
- [RFC v5 13/68] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2020/09/29
- [RFC v5 14/68] target/riscv: rvv-1.0: update check functions, frank . chang, 2020/09/29
- [RFC v5 15/68] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2020/09/29
- [RFC v5 16/68] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2020/09/29
- [RFC v5 17/68] target/riscv: rvv-1.0: configure instructions, frank . chang, 2020/09/29
- [RFC v5 18/68] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2020/09/29
- [RFC v5 19/68] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2020/09/29
- [RFC v5 20/68] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns,
frank . chang <=
- [RFC v5 21/68] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2020/09/29
- [RFC v5 22/68] target/riscv: rvv-1.0: amo operations, frank . chang, 2020/09/29
- [RFC v5 23/68] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/09/29
- [RFC v5 24/68] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/09/29
- [RFC v5 25/68] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/09/29
- [RFC v5 26/68] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2020/09/29
- [RFC v5 27/68] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/09/29
- [RFC v5 28/68] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/09/29
- [RFC v5 29/68] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/09/29
- [RFC v5 30/68] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/09/29