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[PULL 51/66] target/mips: Pass TCGCond argument to MSA gen_check_zero_el
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 51/66] target/mips: Pass TCGCond argument to MSA gen_check_zero_element() |
Date: |
Thu, 7 Jan 2021 23:22:38 +0100 |
Simplify gen_check_zero_element() by passing the TCGCond
argument along.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-25-f4bug@amsat.org>
---
target/mips/msa_translate.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c
index a4f9a6c1285..52bd428759a 100644
--- a/target/mips/msa_translate.c
+++ b/target/mips/msa_translate.c
@@ -304,7 +304,8 @@ static inline int check_msa_access(DisasContext *ctx)
return 1;
}
-static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt)
+static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
+ TCGCond cond)
{
/* generates tcg ops to check if any element is 0 */
/* Note this function only works with MSA_WRLEN = 128 */
@@ -339,7 +340,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_t
df, uint8_t wt)
tcg_gen_or_i64(t0, t0, t1);
/* if all bits are zero then all elements are not zero */
/* if some bit is non-zero then some element is zero */
- tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0);
+ tcg_gen_setcondi_i64(cond, t0, t0, 0);
tcg_gen_trunc_i64_tl(tresult, t0);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
@@ -378,10 +379,7 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt,
int s16, bool if_not)
return true;
}
- gen_check_zero_element(bcond, df, wt);
- if (if_not) {
- tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
- }
+ gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE);
ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
ctx->hflags |= MIPS_HFLAG_BC;
--
2.26.2
- [PULL 41/66] target/mips: Remove now unused ASE_MSA definition, (continued)
- [PULL 41/66] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 42/66] target/mips: Alias MSA vector registers on FPU scalar registers, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 43/66] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 44/66] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 45/66] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 46/66] target/mips: Move msa_reset() to msa_helper.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 47/66] target/mips: Extract MSA helpers from op_helper.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 48/66] target/mips: Extract MSA helper definitions, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 49/66] target/mips: Declare gen_msa/_branch() in 'translate.h', Philippe Mathieu-Daudé, 2021/01/07
- [PULL 50/66] target/mips: Extract MSA translation routines, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 51/66] target/mips: Pass TCGCond argument to MSA gen_check_zero_element(),
Philippe Mathieu-Daudé <=
- [PULL 52/66] target/mips: Introduce decode tree bindings for MSA ASE, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 53/66] target/mips: Use decode_ase_msa() generated from decodetree, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 54/66] target/mips: Extract LSA/DLSA translation generators, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 55/66] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 56/66] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 57/66] target/mips: Remove now unreachable LSA/DLSA opcodes code, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 58/66] target/mips: Convert Rel6 Special2 opcode to decodetree, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 59/66] target/mips: Convert Rel6 COP1X opcode to decodetree, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 60/66] target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 61/66] target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree, Philippe Mathieu-Daudé, 2021/01/07