Re: [PATCH 03/22] tcg: Split out target constraints to tcg-target-constr.h

[Peter Maydell]

On Wed, 23 Dec 2020 at 06:09, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This eliminates the target-specific function target_parse_constraint
> and folds it into the single caller, process_op_defs.  Since this is
> done directly into the switch statement, duplicates are compilation
> errors rather than silently ignored at runtime.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  tcg/i386/tcg-target-constr.h | 26 ++++++++++++++
>  tcg/i386/tcg-target.h        |  1 +
>  tcg/tcg.c                    | 33 ++++++++++++++---
>  tcg/i386/tcg-target.c.inc    | 70 ++----------------------------------
>  4 files changed, 58 insertions(+), 72 deletions(-)
>  create mode 100644 tcg/i386/tcg-target-constr.h
>
> diff --git a/tcg/i386/tcg-target-constr.h b/tcg/i386/tcg-target-constr.h
> new file mode 100644
> index 0000000000..e4a4886b6c
> --- /dev/null
> +++ b/tcg/i386/tcg-target-constr.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * i386 target-specific operand constaints.

"constraints"

> + * Copyright (c) 2020 Linaro
> + */
> +
> +REGS('a', 1u << TCG_REG_EAX)
> +REGS('b', 1u << TCG_REG_EBX)
> +REGS('c', 1u << TCG_REG_ECX)
> +REGS('d', 1u << TCG_REG_EDX)
> +REGS('S', 1u << TCG_REG_ESI)
> +REGS('D', 1u << TCG_REG_EDI)
> +
> +REGS('r', ALL_GENERAL_REGS)
> +REGS('x', ALL_VECTOR_REGS)
> +/* A register that can be used as a byte operand.  */
> +REGS('q', ALL_BYTEL_REGS)
> +/* A register with an addressable second byte (e.g. %ah).  */
> +REGS('Q', ALL_BYTEH_REGS)
> +/* qemu_ld/st address constraint */
> +REGS('L', ALL_GENERAL_REGS & ~((1 << TCG_REG_L0) | (1 << TCG_REG_L1)))
> +
> +CONST('e', TCG_CT_CONST_S32)
> +CONST('I', TCG_CT_CONST_I32)
> +CONST('W', TCG_CT_CONST_WSZ)
> +CONST('Z', TCG_CT_CONST_U32)

This is a little bit less obscure than the conset.h macros,
but it would still be nice to have some documentation of
what's actually going on here.

thanks
-- PMM