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[PULL v2 56/69] target/mips: Introduce decodetree helpers for Release6 L
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL v2 56/69] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes |
Date: |
Thu, 14 Jan 2021 17:20:10 +0100 |
LSA and LDSA opcodes are also available with MIPS release 6.
Introduce the decodetree config files and call the decode()
helpers in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-24-f4bug@amsat.org>
---
target/mips/translate.h | 1 +
target/mips/mips32r6.decode | 17 +++++++++++++++++
target/mips/mips64r6.decode | 17 +++++++++++++++++
target/mips/rel6_translate.c | 37 ++++++++++++++++++++++++++++++++++++
target/mips/translate.c | 5 +++++
target/mips/meson.build | 3 +++
6 files changed, 80 insertions(+)
create mode 100644 target/mips/mips32r6.decode
create mode 100644 target/mips/mips64r6.decode
create mode 100644 target/mips/rel6_translate.c
diff --git a/target/mips/translate.h b/target/mips/translate.h
index f93df0c5ab2..f47b5f2c8d0 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -171,6 +171,7 @@ extern TCGv bcond;
void msa_translate_init(void);
/* decodetree generated */
+bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
#endif
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode
new file mode 100644
index 00000000000..d71a65f32cb
--- /dev/null
+++ b/target/mips/mips32r6.decode
@@ -0,0 +1,17 @@
+# MIPS32 Release 6 instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume II-A
+# The MIPS32 Instruction Set Reference Manual, Revision 6.06
+# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06)
+#
+
+&rtype rs rt rd sa
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
+
+LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
diff --git a/target/mips/mips64r6.decode b/target/mips/mips64r6.decode
new file mode 100644
index 00000000000..fd58ac72414
--- /dev/null
+++ b/target/mips/mips64r6.decode
@@ -0,0 +1,17 @@
+# MIPS64 Release 6 instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume II-A
+# The MIPS64 Instruction Set Reference Manual, Revision 6.06
+# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
+#
+
+&rtype rs rt rd sa !extern
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
+
+DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
diff --git a/target/mips/rel6_translate.c b/target/mips/rel6_translate.c
new file mode 100644
index 00000000000..da70ff9662b
--- /dev/null
+++ b/target/mips/rel6_translate.c
@@ -0,0 +1,37 @@
+/*
+ * MIPS emulation for QEMU - # Release 6 translation routines
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+
+/* Include the auto-generated decoder. */
+#include "decode-mips32r6.c.inc"
+#include "decode-mips64r6.c.inc"
+
+static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
+{
+ return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+static bool trans_DLSA(DisasContext *ctx, arg_rtype *a)
+{
+ return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+bool decode_isa_rel6(DisasContext *ctx, uint32_t insn)
+{
+ if (TARGET_LONG_BITS == 64 && decode_mips64r6(ctx, insn)) {
+ return true;
+ }
+ return decode_mips32r6(ctx, insn);
+}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bed1a286f43..d297029a777 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29025,6 +29025,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
return;
}
+ /* ISA (from latest to oldest) */
+ if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx,
ctx->opcode)) {
+ return;
+ }
+
if (decode_opc_legacy(env, ctx)) {
return;
}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index b63d8f150f1..9741545440c 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,4 +1,6 @@
gen = [
+ decodetree.process('mips32r6.decode', extra_args:
'--static-decode=decode_mips32r6'),
+ decodetree.process('mips64r6.decode', extra_args:
'--static-decode=decode_mips64r6'),
decodetree.process('msa32.decode', extra_args:
'--static-decode=decode_msa32'),
decodetree.process('msa64.decode', extra_args:
'--static-decode=decode_msa64'),
]
@@ -16,6 +18,7 @@
'msa_helper.c',
'msa_translate.c',
'op_helper.c',
+ 'rel6_translate.c',
'tlb_helper.c',
'translate.c',
'translate_addr_const.c',
--
2.26.2
- [PULL v2 30/69] target/mips: Replace gen_exception_err(err=0) by gen_exception_end(), (continued)
- [PULL v2 30/69] target/mips: Replace gen_exception_err(err=0) by gen_exception_end(), Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 31/69] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 32/69] target/mips: Declare generic FPU / Coprocessor functions in translate.h, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 36/69] target/mips/translate: Expose check_mips_64() to 32-bit mode, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 35/69] target/mips/translate: Extract decode_opc_legacy() from decode_opc(), Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 52/69] target/mips: Introduce decode tree bindings for MSA ASE, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 53/69] target/mips: Use decode_ase_msa() generated from decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 54/69] target/mips: Extract LSA/DLSA translation generators, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 55/69] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 58/69] target/mips: Convert Rel6 Special2 opcode to decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 56/69] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes,
Philippe Mathieu-Daudé <=
- [PULL v2 57/69] target/mips: Remove now unreachable LSA/DLSA opcodes code, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 63/69] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 66/69] target/mips: Remove CPU_R5900 definition, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 67/69] target/mips: Remove CPU_NANOMIPS32 definition, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 68/69] target/mips: Remove vendor specific CPU definitions, Philippe Mathieu-Daudé, 2021/01/14
- Re: [PULL v2 00/69] MIPS patches for 2021-01-14, Peter Maydell, 2021/01/15