[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 67/69] target/mips: Remove CPU_NANOMIPS32 definition
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL v2 67/69] target/mips: Remove CPU_NANOMIPS32 definition |
Date: |
Thu, 14 Jan 2021 17:20:15 +0100 |
nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already
defined as ISA_NANOMIPS32.
Remove this incorrect definition and update the single CPU
implementing it, the I7200.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-3-f4bug@amsat.org>
---
target/mips/mips-defs.h | 3 ---
target/mips/cpu-defs.c.inc | 4 ++--
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index b7879be9e90..3704db85532 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -86,9 +86,6 @@
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
-/* Wave Computing: "nanoMIPS" */
-#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
-
#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
/*
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index ba22ff4bcd1..9f7bac87932 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -486,8 +486,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 |
- ASE_MT,
+ .insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 |
+ ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT,
.mmu_type = MMU_TYPE_R4000,
},
#if defined(TARGET_MIPS64)
--
2.26.2
- [PULL v2 35/69] target/mips/translate: Extract decode_opc_legacy() from decode_opc(), (continued)
- [PULL v2 35/69] target/mips/translate: Extract decode_opc_legacy() from decode_opc(), Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 52/69] target/mips: Introduce decode tree bindings for MSA ASE, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 53/69] target/mips: Use decode_ase_msa() generated from decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 54/69] target/mips: Extract LSA/DLSA translation generators, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 55/69] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 58/69] target/mips: Convert Rel6 Special2 opcode to decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 56/69] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 57/69] target/mips: Remove now unreachable LSA/DLSA opcodes code, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 63/69] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 66/69] target/mips: Remove CPU_R5900 definition, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 67/69] target/mips: Remove CPU_NANOMIPS32 definition,
Philippe Mathieu-Daudé <=
- [PULL v2 68/69] target/mips: Remove vendor specific CPU definitions, Philippe Mathieu-Daudé, 2021/01/14
- Re: [PULL v2 00/69] MIPS patches for 2021-01-14, Peter Maydell, 2021/01/15