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[RFC PATCH 06/42] target/mips: Introduce gen_load_gpr_hi() / gen_store_g
From: |
Philippe Mathieu-Daudé |
Subject: |
[RFC PATCH 06/42] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers |
Date: |
Sun, 14 Feb 2021 18:58:36 +0100 |
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 4 ++++
target/mips/translate.c | 18 ++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 3014c20cadb..468e29d7578 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -131,6 +131,10 @@ void gen_move_low32(TCGv ret, TCGv_i64 arg);
void gen_move_high32(TCGv ret, TCGv_i64 arg);
void gen_load_gpr(TCGv t, int reg);
void gen_store_gpr(TCGv t, int reg);
+#if defined(TARGET_MIPS64)
+void gen_load_gpr_hi(TCGv_i64 t, int reg);
+void gen_store_gpr_hi(TCGv_i64 t, int reg);
+#endif /* TARGET_MIPS64 */
void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9c034c934d5..16a731d3f37 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2291,6 +2291,24 @@ void gen_store_gpr(TCGv t, int reg)
}
}
+#if defined(TARGET_MIPS64)
+void gen_load_gpr_hi(TCGv_i64 t, int reg)
+{
+ if (reg == 0) {
+ tcg_gen_movi_i64(t, 0);
+ } else {
+ tcg_gen_mov_i64(t, cpu_gpr_hi[reg]);
+ }
+}
+
+void gen_store_gpr_hi(TCGv_i64 t, int reg)
+{
+ if (reg != 0) {
+ tcg_gen_mov_i64(cpu_gpr_hi[reg], t);
+ }
+}
+#endif /* TARGET_MIPS64 */
+
/* Moves to/from shadow registers. */
static inline void gen_load_srsgpr(int from, int to)
{
--
2.26.2
- [RFC PATCH 00/42] target/mips: Reintroduce the R5900 CPU (with more testing), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 01/42] linux-user/mips64: Restore setup_frame() for o32 ABI, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 02/42] linux-user/mips64: Support o32 ABI syscalls, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 03/42] target/mips/translate: Make cpu_HI/LO registers public, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 04/42] target/mips: Promote 128-bit multimedia registers as global ones, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 05/42] target/mips: Rename 128-bit upper halve GPR registers, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 06/42] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers,
Philippe Mathieu-Daudé <=
- [RFC PATCH 07/42] target/mips/translate: Use GPR move functions in gen_HILO1_tx79(), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 08/42] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 09/42] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 10/42] target/mips/translate: Simplify PCPYH using deposit_i64(), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 11/42] target/mips/tx79: Move PCPYH opcode to decodetree, Philippe Mathieu-Daudé, 2021/02/14