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[RFC PATCH 07/42] target/mips/translate: Use GPR move functions in gen_H
From: |
Philippe Mathieu-Daudé |
Subject: |
[RFC PATCH 07/42] target/mips/translate: Use GPR move functions in gen_HILO1_tx79() |
Date: |
Sun, 14 Feb 2021 18:58:37 +0100 |
We have handy functions to access GPR. Use gen_store_gpr() for
Move From HI/LO Register and gen_load_gpr() for Move To opcodes.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 21 ++++-----------------
1 file changed, 4 insertions(+), 17 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 16a731d3f37..a2994eb0aa6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4126,31 +4126,18 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
/* Copy GPR to and from TX79 HI1/LO1 register. */
static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
{
- if (reg == 0 && (opc == MMI_OPC_MFHI1 || opc == MMI_OPC_MFLO1)) {
- /* Treat as NOP. */
- return;
- }
-
switch (opc) {
case MMI_OPC_MFHI1:
- tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]);
+ gen_store_gpr(cpu_HI[1], reg);
break;
case MMI_OPC_MFLO1:
- tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]);
+ gen_store_gpr(cpu_LO[1], reg);
break;
case MMI_OPC_MTHI1:
- if (reg != 0) {
- tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]);
- } else {
- tcg_gen_movi_tl(cpu_HI[1], 0);
- }
+ gen_load_gpr(cpu_HI[1], reg);
break;
case MMI_OPC_MTLO1:
- if (reg != 0) {
- tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]);
- } else {
- tcg_gen_movi_tl(cpu_LO[1], 0);
- }
+ gen_load_gpr(cpu_LO[1], reg);
break;
default:
MIPS_INVAL("mfthilo1 TX79");
--
2.26.2
- [RFC PATCH 01/42] linux-user/mips64: Restore setup_frame() for o32 ABI, (continued)
- [RFC PATCH 01/42] linux-user/mips64: Restore setup_frame() for o32 ABI, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 02/42] linux-user/mips64: Support o32 ABI syscalls, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 03/42] target/mips/translate: Make cpu_HI/LO registers public, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 04/42] target/mips: Promote 128-bit multimedia registers as global ones, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 05/42] target/mips: Rename 128-bit upper halve GPR registers, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 06/42] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 07/42] target/mips/translate: Use GPR move functions in gen_HILO1_tx79(),
Philippe Mathieu-Daudé <=
- [RFC PATCH 08/42] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 09/42] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 10/42] target/mips/translate: Simplify PCPYH using deposit_i64(), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 11/42] target/mips/tx79: Move PCPYH opcode to decodetree, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 12/42] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree, Philippe Mathieu-Daudé, 2021/02/14