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Re: [PATCH v1 2/8] target/riscv: Define ePMP mseccfg


From: Bin Meng
Subject: Re: [PATCH v1 2/8] target/riscv: Define ePMP mseccfg
Date: Wed, 7 Apr 2021 22:24:22 +0800

On Fri, Apr 2, 2021 at 8:49 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> From: Hou Weiying <weiying_hou@outlook.com>
>
> Use address  0x390 and 0x391 for the ePMP CSRs.

nits: remove one space before 0x390

>
> Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
> Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
> Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Message-Id: 
> <SG2PR02MB2634D85E5DF0C2BB540AE1BB93450@SG2PR02MB2634.apcprd02.prod.outlook.com>
> [ Changes by AF:
>  - Tidy up commit message
> ]
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu_bits.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index caf4599207..32e1ee92dc 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -232,6 +232,9 @@
>  #define CSR_MTINST          0x34a
>  #define CSR_MTVAL2          0x34b
>
> +/* Enhanced PMP */

nits: Enhanced Physical Memory Protection ?

> +#define CSR_MSECCFG         0x390
> +#define CSR_MSECCFGH        0x391
>  /* Physical Memory Protection */
>  #define CSR_PMPCFG0         0x3a0
>  #define CSR_PMPCFG1         0x3a1

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Regards,
Bin



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