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[RFC v13 36/80] target/arm: fix style of arm_cpu_do_interrupt functions
From: |
Claudio Fontana |
Subject: |
[RFC v13 36/80] target/arm: fix style of arm_cpu_do_interrupt functions before move |
Date: |
Wed, 14 Apr 2021 13:26:06 +0200 |
before refactoring the exception code, fix the style of the
functions being moved.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/helper.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index f2407f0af5..9f16af8a68 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -896,10 +896,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
new_mode = ARM_CPU_MODE_UND;
addr = 0x04;
mask = CPSR_I;
- if (env->thumb)
+ if (env->thumb) {
offset = 2;
- else
+ } else {
offset = 4;
+ }
break;
case EXCP_SWI:
new_mode = ARM_CPU_MODE_SVC;
@@ -985,7 +986,8 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
/* High vectors. When enabled, base address cannot be remapped. */
addr += 0xffff0000;
} else {
- /* ARM v7 architectures provide a vector base address register to remap
+ /*
+ * ARM v7 architectures provide a vector base address register to remap
* the interrupt vector table.
* This register is only followed in non-monitor mode, and is banked.
* Note: only bits 31:5 are valid.
@@ -1094,7 +1096,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
if (cur_el < new_el) {
- /* Entry vector offset depends on whether the implemented EL
+ /*
+ * Entry vector offset depends on whether the implemented EL
* immediately lower than the target level is using AArch32 or AArch64
*/
bool is_aa64;
@@ -1285,7 +1288,8 @@ static void handle_semihosting(CPUState *cs)
}
#endif
-/* Handle a CPU exception for A and R profile CPUs.
+/*
+ * Handle a CPU exception for A and R profile CPUs.
* Do any appropriate logging, handle PSCI calls, and then hand off
* to the AArch64-entry or AArch32-entry function depending on the
* target exception level's register width.
@@ -1330,7 +1334,8 @@ void arm_cpu_do_interrupt(CPUState *cs)
}
#endif
- /* Hooks may change global state so BQL should be held, also the
+ /*
+ * Hooks may change global state so BQL should be held, also the
* BQL needs to be held for any modification of
* cs->interrupt_request.
*/
--
2.26.2
- [RFC v13 21/80] target/arm: split vfp state setting from tcg helpers, (continued)
- [RFC v13 21/80] target/arm: split vfp state setting from tcg helpers, Claudio Fontana, 2021/04/14
- [RFC v13 22/80] target/arm: move arm_mmu_idx* to cpu-mmu, Claudio Fontana, 2021/04/14
- [RFC v13 25/80] target/arm: move arm_cpu_list to common_cpu, Claudio Fontana, 2021/04/14
- [RFC v13 27/80] target/arm: new cpu32 ARM 32 bit CPU Class, Claudio Fontana, 2021/04/14
- [RFC v13 14/80] target/arm: split cpregs from tcg/helper.c, Claudio Fontana, 2021/04/14
- [RFC v13 23/80] target/arm: move sve_zcr_len_for_el to common_cpu, Claudio Fontana, 2021/04/14
- [RFC v13 24/80] target/arm: move arm_sctlr away from tcg helpers, Claudio Fontana, 2021/04/14
- [RFC v13 28/80] target/arm: split 32bit and 64bit arm dump state, Claudio Fontana, 2021/04/14
- [RFC v13 33/80] target/arm: move fp_exception_el out of TCG helpers, Claudio Fontana, 2021/04/14
- [RFC v13 31/80] target/arm: move sve_exception_el out of TCG helpers, Claudio Fontana, 2021/04/14
- [RFC v13 36/80] target/arm: fix style of arm_cpu_do_interrupt functions before move,
Claudio Fontana <=
- [RFC v13 42/80] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Claudio Fontana, 2021/04/14
- [RFC v13 40/80] target/arm: move TCGCPUOps to tcg/tcg-cpu.c, Claudio Fontana, 2021/04/14
- [RFC v13 39/80] target/arm: replace CONFIG_TCG with tcg_enabled, Claudio Fontana, 2021/04/14
- [RFC v13 44/80] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/, Claudio Fontana, 2021/04/14
- [RFC v13 26/80] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code, Claudio Fontana, 2021/04/14
- [RFC v13 35/80] target/arm: make further preparation for the exception code to move, Claudio Fontana, 2021/04/14
- [RFC v13 43/80] target/arm: remove kvm include file for PSCI and arm-powerctl, Claudio Fontana, 2021/04/14
- [RFC v13 46/80] target/arm: cleanup cpu includes, Claudio Fontana, 2021/04/14
- [RFC v13 48/80] target/arm: remove kvm-stub.c, Claudio Fontana, 2021/04/14
- [RFC v13 30/80] target/arm: fixup sve_exception_el code style before move, Claudio Fontana, 2021/04/14