Re: [PATCH] target/mips: Migrate missing CPU fields

[Richard Henderson]

On 4/23/21 3:00 PM, Philippe Mathieu-Daudé wrote:
> Add various missing fields to the CPU migration vmstate:
>
> - CP0_VPControl & CP0_GlobalNumber      (01bc435b44b 2016-02-03)
> - CMGCRBase                             (c870e3f52ca 2016-03-15)
> - CP0_ErrCtl                            (0d74a222c27 2016-03-25)
> - MXU GPR[] & CR                        (eb5559f67dc 2018-10-18)
> - R5900 128-bit upper half              (a168a796e1c 2019-01-17)
>
> This is a migration break.
>
> Fixes: 01bc435b44b ("target-mips: implement R6 multi-threading")
> Fixes: c870e3f52ca ("target-mips: add CMGCRBase register")
> Fixes: 0d74a222c27 ("target-mips: make ITC Configuration Tags accessible to the 
> CPU")
> Fixes: eb5559f67dc ("target/mips: Introduce MXU registers")
> Fixes: a168a796e1c ("target/mips: Introduce 32 R5900 multimedia registers")
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/machine.c | 21 +++++++++++++++------
>   1 file changed, 15 insertions(+), 6 deletions(-)

Acked-by: Richard Henderson <richard.henderson@linaro.org>

I didn't review the whole CPUMIPSState, but I agree that everything
that is added should have been listed.


r~