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Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructio
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions |
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Date: |
Mon, 26 Apr 2021 08:58:12 +1000 |
On Sun, Apr 25, 2021 at 3:08 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/23/21 8:34 PM, Alistair Francis wrote:
> > --- a/target/riscv/translate.c
> > +++ b/target/riscv/translate.c
> > @@ -74,8 +74,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t
> > ext)
> >
> > #ifdef TARGET_RISCV32
> > # define is_32bit(ctx) true
> > -#elif defined(CONFIG_USER_ONLY)
> > -# define is_32bit(ctx) false
> > #else
> > static inline bool is_32bit(DisasContext *ctx)
> > {
>
> Rebase error?
This is required to avoid warnings/errors before this commit as
`is_32bit()` isn't called until this patch.
Alistair
>
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~
- [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on, Alistair Francis, 2021/04/23
- [PATCH v3 01/10] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/04/23
- [PATCH v3 02/10] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/04/23
- [PATCH v3 03/10] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/04/23
- [PATCH v3 04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/04/23
- [PATCH v3 05/10] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/04/23
- [PATCH v3 06/10] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/04/23
- [PATCH v3 07/10] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/04/23
- [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/04/23
[PATCH v3 09/10] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/04/23
[PATCH v3 10/10] target/riscv: Fix the RV64H decode comment, Alistair Francis, 2021/04/23
Re: [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on, Alistair Francis, 2021/04/25