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Re: [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment |
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Date: |
Mon, 26 Apr 2021 08:58:28 +1000 |
On Sun, Apr 25, 2021 at 3:14 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/23/21 8:34 PM, Alistair Francis wrote:
> > BugLink: https://gitlab.com/qemu-project/qemu/-/issues/6
>
> The issue got renumbered to 47, fwiw.
Thanks!
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> r~
>
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/insn32.decode | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> > index fecf0f15d5..8901ba1e1b 100644
> > --- a/target/riscv/insn32.decode
> > +++ b/target/riscv/insn32.decode
> > @@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011
> > @r2_s
> > hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
> > hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
> >
> > -# *** RV32H Base Instruction Set ***
> > +# *** RV64H Base Instruction Set ***
> > hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
> > hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
> > hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
> >
>
- [PATCH v3 06/10] target/riscv: Remove the unused HSTATUS_WPRI macro, (continued)
[PATCH v3 09/10] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/04/23
[PATCH v3 10/10] target/riscv: Fix the RV64H decode comment, Alistair Francis, 2021/04/23
Re: [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on, Alistair Francis, 2021/04/25