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[PULL 01/43] hw/arm/smmuv3: Support 16K translation granule
From: |
Peter Maydell |
Subject: |
[PULL 01/43] hw/arm/smmuv3: Support 16K translation granule |
Date: |
Fri, 30 Apr 2021 11:33:55 +0100 |
From: Kunkun Jiang <jiangkunkun@huawei.com>
The driver can query some bits in SMMUv3 IDR5 to learn which
translation granules are supported. Arm recommends that SMMUv3
implementations support at least 4K and 64K granules. But in
the vSMMUv3, there seems to be no reason not to support 16K
translation granule. In addition, if 16K is not supported,
vSVA will failed to be enabled in the future for 16K guest
kernel. So it'd better to support it.
Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/smmuv3.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 87056125357..228dc54b0bc 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -259,8 +259,9 @@ static void smmuv3_init_regs(SMMUv3State *s)
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
- /* 4K and 64K granule support */
+ /* 4K, 16K and 64K granule support */
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
+ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1);
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
@@ -503,7 +504,8 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd,
SMMUEventInfo *event)
tg = CD_TG(cd, i);
tt->granule_sz = tg2granule(tg, i);
- if ((tt->granule_sz != 12 && tt->granule_sz != 16) || CD_ENDI(cd)) {
+ if ((tt->granule_sz != 12 && tt->granule_sz != 14 &&
+ tt->granule_sz != 16) || CD_ENDI(cd)) {
goto bad_cd;
}
--
2.20.1
- [PULL 00/43] target-arm queue, Peter Maydell, 2021/04/30
- [PULL 01/43] hw/arm/smmuv3: Support 16K translation granule,
Peter Maydell <=
- [PULL 02/43] target/arm: Make Thumb store insns UNDEF for Rn==1111, Peter Maydell, 2021/04/30
- [PULL 03/43] target/arm: Fix mte_checkN, Peter Maydell, 2021/04/30
- [PULL 04/43] target/arm: Split out mte_probe_int, Peter Maydell, 2021/04/30
- [PULL 06/43] test/tcg/aarch64: Add mte-5, Peter Maydell, 2021/04/30
- [PULL 05/43] target/arm: Fix unaligned checks for mte_check1, mte_probe1, Peter Maydell, 2021/04/30
- [PULL 11/43] target/arm: Remove log2_esize parameter to gen_mte_checkN, Peter Maydell, 2021/04/30
- [PULL 07/43] target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1, Peter Maydell, 2021/04/30
- [PULL 12/43] target/arm: Fix decode of align in VLDST_single, Peter Maydell, 2021/04/30
- [PULL 13/43] target/arm: Rename TBFLAG_A32, SCTLR_B, Peter Maydell, 2021/04/30
- [PULL 09/43] target/arm: Rename mte_probe1 to mte_probe, Peter Maydell, 2021/04/30