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[PULL 02/43] target/arm: Make Thumb store insns UNDEF for Rn==1111
From: |
Peter Maydell |
Subject: |
[PULL 02/43] target/arm: Make Thumb store insns UNDEF for Rn==1111 |
Date: |
Fri, 30 Apr 2021 11:33:56 +0100 |
The Arm ARM specifies that for Thumb encodings of the various plain
store insns, if the Rn field is 1111 then we must UNDEF. This is
different from the Arm encodings, where this case is either
UNPREDICTABLE or has well-defined behaviour. The exclusive stores,
store-release and STRD do not have this UNDEF case for any encoding.
Enforce the UNDEF for this case in the Thumb plain store insns.
Fixes: https://bugs.launchpad.net/qemu/+bug/1922887
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210408162402.5822-1-peter.maydell@linaro.org
---
target/arm/translate.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7103da2d7ab..68809e08f09 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6476,6 +6476,14 @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a,
ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite;
TCGv_i32 addr, tmp;
+ /*
+ * In Thumb encodings of stores Rn=1111 is UNDEF; for Arm it
+ * is either UNPREDICTABLE or has defined behaviour
+ */
+ if (s->thumb && a->rn == 15) {
+ return false;
+ }
+
addr = op_addr_rr_pre(s, a);
tmp = load_reg(s, a->rt);
@@ -6620,6 +6628,14 @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a,
ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite;
TCGv_i32 addr, tmp;
+ /*
+ * In Thumb encodings of stores Rn=1111 is UNDEF; for Arm it
+ * is either UNPREDICTABLE or has defined behaviour
+ */
+ if (s->thumb && a->rn == 15) {
+ return false;
+ }
+
addr = op_addr_ri_pre(s, a);
tmp = load_reg(s, a->rt);
--
2.20.1
- [PULL 00/43] target-arm queue, Peter Maydell, 2021/04/30
- [PULL 01/43] hw/arm/smmuv3: Support 16K translation granule, Peter Maydell, 2021/04/30
- [PULL 02/43] target/arm: Make Thumb store insns UNDEF for Rn==1111,
Peter Maydell <=
- [PULL 03/43] target/arm: Fix mte_checkN, Peter Maydell, 2021/04/30
- [PULL 04/43] target/arm: Split out mte_probe_int, Peter Maydell, 2021/04/30
- [PULL 06/43] test/tcg/aarch64: Add mte-5, Peter Maydell, 2021/04/30
- [PULL 05/43] target/arm: Fix unaligned checks for mte_check1, mte_probe1, Peter Maydell, 2021/04/30
- [PULL 11/43] target/arm: Remove log2_esize parameter to gen_mte_checkN, Peter Maydell, 2021/04/30
- [PULL 07/43] target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1, Peter Maydell, 2021/04/30
- [PULL 12/43] target/arm: Fix decode of align in VLDST_single, Peter Maydell, 2021/04/30
- [PULL 13/43] target/arm: Rename TBFLAG_A32, SCTLR_B, Peter Maydell, 2021/04/30
- [PULL 09/43] target/arm: Rename mte_probe1 to mte_probe, Peter Maydell, 2021/04/30
- [PULL 08/43] target/arm: Merge mte_check1, mte_checkN, Peter Maydell, 2021/04/30