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[PULL 18/43] target/arm: Move TBFLAG_AM32 bits to the top
From: |
Peter Maydell |
Subject: |
[PULL 18/43] target/arm: Move TBFLAG_AM32 bits to the top |
Date: |
Fri, 30 Apr 2021 11:34:12 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Now that these bits have been moved out of tb->flags,
where TBFLAG_ANY was filling from the top, move AM32
to fill from the top, and A32 and M32 to fill from the
bottom. This means fewer changes when adding new bits.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 42 +++++++++++++++++++++---------------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a8da7c55a6b..15104e14409 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3395,13 +3395,13 @@ typedef ARMCPU ArchCPU;
*
* The bits for 32-bit A-profile and M-profile partially overlap:
*
- * 18 9 0
- * +----------------+--------------+
- * | TBFLAG_A32 | |
- * +-----+----------+ TBFLAG_AM32 |
- * | |TBFLAG_M32| |
- * +-----+----------+--------------+
- * 14 9 0
+ * 31 23 11 10 0
+ * +-------------+----------+----------------+
+ * | | | TBFLAG_A32 |
+ * | TBFLAG_AM32 | +-----+----------+
+ * | | |TBFLAG_M32|
+ * +-------------+----------------+----------+
+ * 31 23 5 4 0
*
* Unless otherwise noted, these bits are cached in env->hflags.
*/
@@ -3418,44 +3418,44 @@ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
/*
* Bit usage when in AArch32 state, both A- and M-profile.
*/
-FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */
-FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */
+FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */
+FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */
/*
* Bit usage when in AArch32 state, for A-profile only.
*/
-FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */
-FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */
+FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */
+FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */
/*
* We store the bottom two bits of the CPAR as TB flags and handle
* checks on the other bits at runtime. This shares the same bits as
* VECSTRIDE, which is OK as no XScale CPU has VFP.
* Not cached, because VECLEN+VECSTRIDE are not cached.
*/
-FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
-FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */
-FIELD(TBFLAG_A32, SCTLR__B, 15, 1) /* Cannot overlap with SCTLR_B */
-FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
+FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2)
+FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */
+FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */
+FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
/*
* Indicates whether cp register reads and writes by guest code should access
* the secure or nonsecure bank of banked registers; note that this is not
* the same thing as the current security state of the processor!
*/
-FIELD(TBFLAG_A32, NS, 17, 1)
+FIELD(TBFLAG_A32, NS, 10, 1)
/*
* Bit usage when in AArch32 state, for M-profile only.
*/
/* Handler (ie not Thread) mode */
-FIELD(TBFLAG_M32, HANDLER, 9, 1)
+FIELD(TBFLAG_M32, HANDLER, 0, 1)
/* Whether we should generate stack-limit checks */
-FIELD(TBFLAG_M32, STACKCHECK, 10, 1)
+FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
/* Set if FPCCR.LSPACT is set */
-FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */
+FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */
/* Set if we must create a new FP context */
-FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */
+FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */
/* Set if FPCCR.S does not match current security state */
-FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */
+FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */
/*
* Bit usage when in AArch64 state
--
2.20.1
- [PULL 09/43] target/arm: Rename mte_probe1 to mte_probe, (continued)
- [PULL 09/43] target/arm: Rename mte_probe1 to mte_probe, Peter Maydell, 2021/04/30
- [PULL 08/43] target/arm: Merge mte_check1, mte_checkN, Peter Maydell, 2021/04/30
- [PULL 10/43] target/arm: Simplify sve mte checking, Peter Maydell, 2021/04/30
- [PULL 14/43] target/arm: Rename TBFLAG_ANY, PSTATE_SS, Peter Maydell, 2021/04/30
- [PULL 15/43] target/arm: Add wrapper macros for accessing tbflags, Peter Maydell, 2021/04/30
- [PULL 17/43] target/arm: Move mode specific TB flags to tb->cs_base, Peter Maydell, 2021/04/30
- [PULL 19/43] target/arm: Move TBFLAG_ANY bits to the bottom, Peter Maydell, 2021/04/30
- [PULL 20/43] target/arm: Add ALIGN_MEM to TBFLAG_ANY, Peter Maydell, 2021/04/30
- [PULL 21/43] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness, Peter Maydell, 2021/04/30
- [PULL 26/43] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, Peter Maydell, 2021/04/30
- [PULL 18/43] target/arm: Move TBFLAG_AM32 bits to the top,
Peter Maydell <=
- [PULL 22/43] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64, Peter Maydell, 2021/04/30
- [PULL 25/43] target/arm: Enforce word alignment for LDRD/STRD, Peter Maydell, 2021/04/30
- [PULL 29/43] target/arm: Enforce alignment for SRS, Peter Maydell, 2021/04/30
- [PULL 16/43] target/arm: Introduce CPUARMTBFlags, Peter Maydell, 2021/04/30
- [PULL 24/43] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness, Peter Maydell, 2021/04/30
- [PULL 31/43] target/arm: Enforce alignment for VLDR/VSTR, Peter Maydell, 2021/04/30
- [PULL 28/43] target/arm: Enforce alignment for RFE, Peter Maydell, 2021/04/30
- [PULL 34/43] target/arm: Enforce alignment for VLDn/VSTn (single), Peter Maydell, 2021/04/30
- [PULL 39/43] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple), Peter Maydell, 2021/04/30
- [PULL 36/43] target/arm: Use finalize_memop for aa64 fpr load/store, Peter Maydell, 2021/04/30