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[PULL 39/43] target/arm: Enforce alignment for aa64 vector LDn/STn (mult
From: |
Peter Maydell |
Subject: |
[PULL 39/43] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) |
Date: |
Fri, 30 Apr 2021 11:34:33 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d3bda16ecd8..2a82dbbd6d4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3635,7 +3635,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
bool is_postidx = extract32(insn, 23, 1);
bool is_q = extract32(insn, 30, 1);
TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
- MemOp endian = s->be_data;
+ MemOp endian, align, mop;
int total; /* total bytes */
int elements; /* elements per vector */
@@ -3703,6 +3703,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
}
/* For our purposes, bytes are always little-endian. */
+ endian = s->be_data;
if (size == 0) {
endian = MO_LE;
}
@@ -3721,11 +3722,17 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
* Consecutive little-endian elements from a single register
* can be promoted to a larger little-endian operation.
*/
+ align = MO_ALIGN;
if (selem == 1 && endian == MO_LE) {
+ align = pow2_align(size);
size = 3;
}
- elements = (is_q ? 16 : 8) >> size;
+ if (!s->align_mem) {
+ align = 0;
+ }
+ mop = endian | size | align;
+ elements = (is_q ? 16 : 8) >> size;
tcg_ebytes = tcg_const_i64(1 << size);
for (r = 0; r < rpt; r++) {
int e;
@@ -3734,9 +3741,9 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
for (xs = 0; xs < selem; xs++) {
int tt = (rt + r + xs) % 32;
if (is_store) {
- do_vec_st(s, tt, e, clean_addr, size | endian);
+ do_vec_st(s, tt, e, clean_addr, mop);
} else {
- do_vec_ld(s, tt, e, clean_addr, size | endian);
+ do_vec_ld(s, tt, e, clean_addr, mop);
}
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
}
--
2.20.1
- [PULL 26/43] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, (continued)
- [PULL 26/43] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, Peter Maydell, 2021/04/30
- [PULL 18/43] target/arm: Move TBFLAG_AM32 bits to the top, Peter Maydell, 2021/04/30
- [PULL 22/43] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64, Peter Maydell, 2021/04/30
- [PULL 25/43] target/arm: Enforce word alignment for LDRD/STRD, Peter Maydell, 2021/04/30
- [PULL 29/43] target/arm: Enforce alignment for SRS, Peter Maydell, 2021/04/30
- [PULL 16/43] target/arm: Introduce CPUARMTBFlags, Peter Maydell, 2021/04/30
- [PULL 24/43] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness, Peter Maydell, 2021/04/30
- [PULL 31/43] target/arm: Enforce alignment for VLDR/VSTR, Peter Maydell, 2021/04/30
- [PULL 28/43] target/arm: Enforce alignment for RFE, Peter Maydell, 2021/04/30
- [PULL 34/43] target/arm: Enforce alignment for VLDn/VSTn (single), Peter Maydell, 2021/04/30
- [PULL 39/43] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple),
Peter Maydell <=
- [PULL 36/43] target/arm: Use finalize_memop for aa64 fpr load/store, Peter Maydell, 2021/04/30
- [PULL 35/43] target/arm: Use finalize_memop for aa64 gpr load/store, Peter Maydell, 2021/04/30
- [PULL 40/43] target/arm: Enforce alignment for aa64 vector LDn/STn (single), Peter Maydell, 2021/04/30
- [PULL 43/43] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows, Peter Maydell, 2021/04/30
- [PULL 41/43] target/arm: Enforce alignment for sve LD1R, Peter Maydell, 2021/04/30
- [PULL 30/43] target/arm: Enforce alignment for VLDM/VSTM, Peter Maydell, 2021/04/30
- [PULL 23/43] target/arm: Fix SCTLR_B test for TCGv_i64 load/store, Peter Maydell, 2021/04/30
- [PULL 33/43] target/arm: Enforce alignment for VLDn/VSTn (multiple), Peter Maydell, 2021/04/30
- [PULL 32/43] target/arm: Enforce alignment for VLDn (all lanes), Peter Maydell, 2021/04/30
- [PULL 37/43] target/arm: Enforce alignment for aa64 load-acq/store-rel, Peter Maydell, 2021/04/30