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[PULL 23/43] target/arm: Fix SCTLR_B test for TCGv_i64 load/store
From: |
Peter Maydell |
Subject: |
[PULL 23/43] target/arm: Fix SCTLR_B test for TCGv_i64 load/store |
Date: |
Fri, 30 Apr 2021 11:34:17 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Just because operating on a TCGv_i64 temporary does not
mean that we're performing a 64-bit operation. Restrict
the frobbing to actual 64-bit operations.
This bug is not currently visible because all current
users of these two functions always pass MO_64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 2f2a6d76b40..e99c0ab5cb9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -982,7 +982,7 @@ static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val,
TCGv_i32 a32,
tcg_gen_qemu_ld_i64(val, addr, index, opc);
/* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b) {
+ if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
tcg_gen_rotri_i64(val, val, 32);
}
@@ -1001,7 +1001,7 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64
val, TCGv_i32 a32,
TCGv addr = gen_aa32_addr(s, a32, opc);
/* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b) {
+ if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_rotri_i64(tmp, val, 32);
tcg_gen_qemu_st_i64(tmp, addr, index, opc);
--
2.20.1
- [PULL 31/43] target/arm: Enforce alignment for VLDR/VSTR, (continued)
- [PULL 31/43] target/arm: Enforce alignment for VLDR/VSTR, Peter Maydell, 2021/04/30
- [PULL 28/43] target/arm: Enforce alignment for RFE, Peter Maydell, 2021/04/30
- [PULL 34/43] target/arm: Enforce alignment for VLDn/VSTn (single), Peter Maydell, 2021/04/30
- [PULL 39/43] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple), Peter Maydell, 2021/04/30
- [PULL 36/43] target/arm: Use finalize_memop for aa64 fpr load/store, Peter Maydell, 2021/04/30
- [PULL 35/43] target/arm: Use finalize_memop for aa64 gpr load/store, Peter Maydell, 2021/04/30
- [PULL 40/43] target/arm: Enforce alignment for aa64 vector LDn/STn (single), Peter Maydell, 2021/04/30
- [PULL 43/43] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows, Peter Maydell, 2021/04/30
- [PULL 41/43] target/arm: Enforce alignment for sve LD1R, Peter Maydell, 2021/04/30
- [PULL 30/43] target/arm: Enforce alignment for VLDM/VSTM, Peter Maydell, 2021/04/30
- [PULL 23/43] target/arm: Fix SCTLR_B test for TCGv_i64 load/store,
Peter Maydell <=
- [PULL 33/43] target/arm: Enforce alignment for VLDn/VSTn (multiple), Peter Maydell, 2021/04/30
- [PULL 32/43] target/arm: Enforce alignment for VLDn (all lanes), Peter Maydell, 2021/04/30
- [PULL 37/43] target/arm: Enforce alignment for aa64 load-acq/store-rel, Peter Maydell, 2021/04/30
- [PULL 38/43] target/arm: Use MemOp for size + endian in aa64 vector ld/st, Peter Maydell, 2021/04/30
- [PULL 27/43] target/arm: Enforce alignment for LDM/STM, Peter Maydell, 2021/04/30
- [PULL 42/43] hw: add compat machines for 6.1, Peter Maydell, 2021/04/30
- Re: [PULL 00/43] target-arm queue, no-reply, 2021/04/30
- Re: [PULL 00/43] target-arm queue, Peter Maydell, 2021/04/30