Re: [PULL 00/43] target-arm queue

[no-reply]

Patchew URL: 
20210430103437.4140-1-peter.maydell@linaro.org/">https://patchew.org/QEMU/20210430103437.4140-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210430103437.4140-1-peter.maydell@linaro.org
Subject: [PULL 00/43] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20210430103437.4140-1-peter.maydell@linaro.org -> 
patchew/20210430103437.4140-1-peter.maydell@linaro.org
Switched to a new branch 'test'
c10b703 hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
d183bcd hw: add compat machines for 6.1
d5e50bf target/arm: Enforce alignment for sve LD1R
d869f59 target/arm: Enforce alignment for aa64 vector LDn/STn (single)
042b95d target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)
3235b6d target/arm: Use MemOp for size + endian in aa64 vector ld/st
3183b95 target/arm: Enforce alignment for aa64 load-acq/store-rel
4b37489 target/arm: Use finalize_memop for aa64 fpr load/store
fea8c48 target/arm: Use finalize_memop for aa64 gpr load/store
0e0f208 target/arm: Enforce alignment for VLDn/VSTn (single)
bfbf212 target/arm: Enforce alignment for VLDn/VSTn (multiple)
69ceac0 target/arm: Enforce alignment for VLDn (all lanes)
abea3ae target/arm: Enforce alignment for VLDR/VSTR
ad20aa0 target/arm: Enforce alignment for VLDM/VSTM
3efa342 target/arm: Enforce alignment for SRS
29302d5 target/arm: Enforce alignment for RFE
f60e412 target/arm: Enforce alignment for LDM/STM
0063d37 target/arm: Enforce alignment for LDA/LDAH/STL/STLH
3f38c99 target/arm: Enforce word alignment for LDRD/STRD
f2dddb4 target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness
464fef2 target/arm: Fix SCTLR_B test for TCGv_i64 load/store
392b70b target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64
6de378e target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness
f815f73 target/arm: Add ALIGN_MEM to TBFLAG_ANY
ff928e9 target/arm: Move TBFLAG_ANY bits to the bottom
f8496e6 target/arm: Move TBFLAG_AM32 bits to the top
6decc8a target/arm: Move mode specific TB flags to tb->cs_base
e3bfd07 target/arm: Introduce CPUARMTBFlags
10530fd target/arm: Add wrapper macros for accessing tbflags
76da347 target/arm: Rename TBFLAG_ANY, PSTATE_SS
b22deaf target/arm: Rename TBFLAG_A32, SCTLR_B
6830495 target/arm: Fix decode of align in VLDST_single
a2b4afa target/arm: Remove log2_esize parameter to gen_mte_checkN
2b5ca84 target/arm: Simplify sve mte checking
35650ce target/arm: Rename mte_probe1 to mte_probe
6670a98 target/arm: Merge mte_check1, mte_checkN
e3efeff target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1
5d77936 test/tcg/aarch64: Add mte-5
bd1040b target/arm: Fix unaligned checks for mte_check1, mte_probe1
47ef13d target/arm: Split out mte_probe_int
4b964fe target/arm: Fix mte_checkN
abac5be target/arm: Make Thumb store insns UNDEF for Rn==1111
45f29da hw/arm/smmuv3: Support 16K translation granule

=== OUTPUT BEGIN ===
1/43 Checking commit 45f29da343f9 (hw/arm/smmuv3: Support 16K translation 
granule)
2/43 Checking commit abac5beadd27 (target/arm: Make Thumb store insns UNDEF for 
Rn==1111)
3/43 Checking commit 4b964fec517c (target/arm: Fix mte_checkN)
4/43 Checking commit 47ef13d29cab (target/arm: Split out mte_probe_int)
5/43 Checking commit bd1040b75897 (target/arm: Fix unaligned checks for 
mte_check1, mte_probe1)
6/43 Checking commit 5d779360a65a (test/tcg/aarch64: Add mte-5)
Use of uninitialized value $acpi_testexpected in string eq at 
./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#32: 
new file mode 100644

total: 0 errors, 1 warnings, 52 lines checked

Patch 6/43 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/43 Checking commit e3efeff2488c (target/arm: Replace MTEDESC ESIZE+TSIZE with 
SIZEM1)
8/43 Checking commit 6670a9856a21 (target/arm: Merge mte_check1, mte_checkN)
9/43 Checking commit 35650cefe675 (target/arm: Rename mte_probe1 to mte_probe)
10/43 Checking commit 2b5ca840dd79 (target/arm: Simplify sve mte checking)
ERROR: spaces required around that '*' (ctx:WxV)
#98: FILE: target/arm/sve_helper.c:4438:
+               sve_ldst1_tlb_fn *tlb_fn)
                                 ^

ERROR: spaces required around that '*' (ctx:WxV)
#192: FILE: target/arm/sve_helper.c:5063:
+               sve_ldst1_tlb_fn *tlb_fn)
                                 ^

total: 2 errors, 0 warnings, 202 lines checked

Patch 10/43 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

11/43 Checking commit a2b4afa35e74 (target/arm: Remove log2_esize parameter to 
gen_mte_checkN)
12/43 Checking commit 6830495b5cb5 (target/arm: Fix decode of align in 
VLDST_single)
13/43 Checking commit b22deaf3400f (target/arm: Rename TBFLAG_A32, SCTLR_B)
14/43 Checking commit 76da34769f23 (target/arm: Rename TBFLAG_ANY, PSTATE_SS)
15/43 Checking commit 10530fd5c629 (target/arm: Add wrapper macros for 
accessing tbflags)
16/43 Checking commit e3bfd07b2839 (target/arm: Introduce CPUARMTBFlags)
17/43 Checking commit 6decc8ab1937 (target/arm: Move mode specific TB flags to 
tb->cs_base)
18/43 Checking commit f8496e673a94 (target/arm: Move TBFLAG_AM32 bits to the 
top)
19/43 Checking commit ff928e971aa6 (target/arm: Move TBFLAG_ANY bits to the 
bottom)
20/43 Checking commit f815f737c4a8 (target/arm: Add ALIGN_MEM to TBFLAG_ANY)
21/43 Checking commit 6de378e63977 (target/arm: Adjust gen_aa32_{ld, st}_i32 
for align+endianness)
22/43 Checking commit 392b70b8b314 (target/arm: Merge gen_aa32_frob64 into 
gen_aa32_ld_i64)
23/43 Checking commit 464fef229153 (target/arm: Fix SCTLR_B test for TCGv_i64 
load/store)
24/43 Checking commit f2dddb4dd46a (target/arm: Adjust gen_aa32_{ld, st}_i64 
for align+endianness)
25/43 Checking commit 3f38c998338d (target/arm: Enforce word alignment for 
LDRD/STRD)
26/43 Checking commit 0063d37bcec2 (target/arm: Enforce alignment for 
LDA/LDAH/STL/STLH)
27/43 Checking commit f60e412d5509 (target/arm: Enforce alignment for LDM/STM)
28/43 Checking commit 29302d5e84e7 (target/arm: Enforce alignment for RFE)
29/43 Checking commit 3efa342d4d58 (target/arm: Enforce alignment for SRS)
30/43 Checking commit ad20aa01b537 (target/arm: Enforce alignment for VLDM/VSTM)
31/43 Checking commit abea3ae25732 (target/arm: Enforce alignment for VLDR/VSTR)
32/43 Checking commit 69ceac0fda93 (target/arm: Enforce alignment for VLDn (all 
lanes))
33/43 Checking commit bfbf212fac92 (target/arm: Enforce alignment for VLDn/VSTn 
(multiple))
34/43 Checking commit 0e0f2085ad13 (target/arm: Enforce alignment for VLDn/VSTn 
(single))
35/43 Checking commit fea8c489c920 (target/arm: Use finalize_memop for aa64 gpr 
load/store)
36/43 Checking commit 4b374892e087 (target/arm: Use finalize_memop for aa64 fpr 
load/store)
37/43 Checking commit 3183b954f17b (target/arm: Enforce alignment for aa64 
load-acq/store-rel)
38/43 Checking commit 3235b6d90615 (target/arm: Use MemOp for size + endian in 
aa64 vector ld/st)
39/43 Checking commit 042b95de4109 (target/arm: Enforce alignment for aa64 
vector LDn/STn (multiple))
40/43 Checking commit d869f59d2dbd (target/arm: Enforce alignment for aa64 
vector LDn/STn (single))
41/43 Checking commit d5e50bf5702c (target/arm: Enforce alignment for sve LD1R)
42/43 Checking commit d183bcd723d1 (hw: add compat machines for 6.1)
43/43 Checking commit c10b703bc1e0 (hw/pci-host/gpex: Don't fault for unmapped 
parts of MMIO and PIO windows)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
20210430103437.4140-1-peter.maydell@linaro.org/testing.checkpatch/?type=message">http://patchew.org/logs/20210430103437.4140-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
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