[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 37/51] hw/arm/stm32f100: Wire up sysclk and refclk
From: |
Peter Maydell |
Subject: |
[PULL 37/51] hw/arm/stm32f100: Wire up sysclk and refclk |
Date: |
Wed, 1 Sep 2021 11:36:39 +0100 |
Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always
runs the systick refclk at 1/8 the frequency of the main CPU clock,
so the board code only needs to provide a single sysclk clock.
Because there is only one board using this SoC, we convert the SoC
and the board together, rather than splitting it into "add clock to
SoC; connect clock in board; add error check in SoC code that clock
is wired up".
When the systick device starts honouring its clock inputs, this will
fix an emulation inaccuracy in the stm32vldiscovery board where the
systick reference clock was running at 1MHz rather than 3MHz.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-12-peter.maydell@linaro.org
---
include/hw/arm/stm32f100_soc.h | 4 ++++
hw/arm/stm32f100_soc.c | 30 ++++++++++++++++++++++++++++++
hw/arm/stm32vldiscovery.c | 12 +++++++-----
3 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
index b7d71c6c634..40cd415b284 100644
--- a/include/hw/arm/stm32f100_soc.h
+++ b/include/hw/arm/stm32f100_soc.h
@@ -29,6 +29,7 @@
#include "hw/ssi/stm32f2xx_spi.h"
#include "hw/arm/armv7m.h"
#include "qom/object.h"
+#include "hw/clock.h"
#define TYPE_STM32F100_SOC "stm32f100-soc"
OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
@@ -56,6 +57,9 @@ struct STM32F100State {
MemoryRegion sram;
MemoryRegion flash;
MemoryRegion flash_alias;
+
+ Clock *sysclk;
+ Clock *refclk;
};
#endif
diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
index 0be92b2c475..f7b344ba9fb 100644
--- a/hw/arm/stm32f100_soc.c
+++ b/hw/arm/stm32f100_soc.c
@@ -30,6 +30,7 @@
#include "exec/address-spaces.h"
#include "hw/arm/stm32f100_soc.h"
#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
#include "hw/misc/unimp.h"
#include "sysemu/sysemu.h"
@@ -57,6 +58,9 @@ static void stm32f100_soc_initfn(Object *obj)
for (i = 0; i < STM_NUM_SPIS; i++) {
object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
}
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+ s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
}
static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -68,6 +72,30 @@ static void stm32f100_soc_realize(DeviceState *dev_soc,
Error **errp)
MemoryRegion *system_memory = get_system_memory();
+ /*
+ * We use s->refclk internally and only define it with qdev_init_clock_in()
+ * so it is correctly parented and not leaked on an init/deinit; it is not
+ * intended as an externally exposed clock.
+ */
+ if (clock_has_source(s->refclk)) {
+ error_setg(errp, "refclk clock must not be wired up by the board
code");
+ return;
+ }
+
+ if (!clock_has_source(s->sysclk)) {
+ error_setg(errp, "sysclk clock must be wired up by the board code");
+ return;
+ }
+
+ /*
+ * TODO: ideally we should model the SoC RCC and its ability to
+ * change the sysclk frequency and define different sysclk sources.
+ */
+
+ /* The refclk always runs at frequency HCLK / 8 */
+ clock_set_mul_div(s->refclk, 8, 1);
+ clock_set_source(s->refclk, s->sysclk);
+
/*
* Init flash region
* Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
@@ -89,6 +117,8 @@ static void stm32f100_soc_realize(DeviceState *dev_soc,
Error **errp)
qdev_prop_set_uint32(armv7m, "num-irq", 61);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
qdev_prop_set_bit(armv7m, "enable-bitband", true);
+ qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
+ qdev_connect_clock_in(armv7m, "refclk", s->refclk);
object_property_set_link(OBJECT(&s->armv7m), "memory",
OBJECT(get_system_memory()), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 7e8191ebf5f..07e401a818d 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -27,6 +27,7 @@
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
#include "qemu/error-report.h"
#include "hw/arm/stm32f100_soc.h"
#include "hw/arm/boot.h"
@@ -39,16 +40,17 @@
static void stm32vldiscovery_init(MachineState *machine)
{
DeviceState *dev;
+ Clock *sysclk;
- /*
- * TODO: ideally we would model the SoC RCC and let it handle
- * system_clock_scale, including its ability to define different
- * possible SYSCLK sources.
- */
system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
+ /* This clock doesn't need migration because it is fixed-frequency */
+ sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(sysclk, SYSCLK_FRQ);
+
dev = qdev_new(TYPE_STM32F100_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
+ qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu),
--
2.20.1
- [PULL 22/51] target/arm: Implement MVE VRINT insns, (continued)
- [PULL 22/51] target/arm: Implement MVE VRINT insns, Peter Maydell, 2021/09/01
- [PULL 06/51] target/arm: Implement MVE VADD (floating-point), Peter Maydell, 2021/09/01
- [PULL 20/51] target/arm: Implement MVE VCVT with specified rounding mode, Peter Maydell, 2021/09/01
- [PULL 24/51] target-arm: Add support for Fujitsu A64FX, Peter Maydell, 2021/09/01
- [PULL 16/51] target/arm: Implement MVE fp vector comparisons, Peter Maydell, 2021/09/01
- [PULL 19/51] target/arm: Implement MVE VCVT between fp and integer, Peter Maydell, 2021/09/01
- [PULL 33/51] armsse: Wire up systick cpuclk clock, Peter Maydell, 2021/09/01
- [PULL 30/51] hw/timer/armv7m_systick: Add usual QEMU interface comment, Peter Maydell, 2021/09/01
- [PULL 36/51] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize, Peter Maydell, 2021/09/01
- [PULL 39/51] hw/arm/stm32f405: Wire up sysclk and refclk, Peter Maydell, 2021/09/01
- [PULL 37/51] hw/arm/stm32f100: Wire up sysclk and refclk,
Peter Maydell <=
- [PULL 43/51] hw/arm/stellaris: Wire sysclk up to armv7m, Peter Maydell, 2021/09/01
- [PULL 35/51] clock: Provide builtin multiplier/divider, Peter Maydell, 2021/09/01
- [PULL 34/51] hw/arm/mps2.c: Connect up armv7m clocks, Peter Maydell, 2021/09/01
- [PULL 45/51] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property, Peter Maydell, 2021/09/01
- [PULL 41/51] hw/arm/nrf51: Wire up sysclk, Peter Maydell, 2021/09/01
- [PULL 48/51] hw/arm/stellaris: Fix code style issues in GPTM code, Peter Maydell, 2021/09/01
- [PULL 46/51] hw/arm/msf2-soc: Wire up refclk, Peter Maydell, 2021/09/01
- [PULL 23/51] target/arm: Enable MVE in Cortex-M55, Peter Maydell, 2021/09/01
- [PULL 25/51] hw/arm/virt: target-arm: Add A64FX processor support to virt machine, Peter Maydell, 2021/09/01
- [PULL 28/51] arm: Move systick device creation from NVIC to ARMv7M object, Peter Maydell, 2021/09/01