Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instr

qemu-devel

From:	Richard Henderson
Subject:	Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction
Date:	Fri, 3 Sep 2021 19:04:37 +0200
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 9/3/21 1:23 AM, Alistair Francis wrote:

+    target_ulong bins;


Surely uint32_t, at least until 64-bit insn width is required.

+    TCGv tmp = temp_new(ctx);
+
+    tcg_gen_movi_tl(tmp, ctx->opcode);
+    tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, bins));


  tcg_gen_st_i32(tcg_constant_i32(ctx->opcode),
                 cpu_env, offsetof(CPURISCVState, bins));


r~

Current Thread

[Next in Thread]

[PATCH v1 0/2] RISC-V: Populate mtval and stval, Alistair Francis, 2021/09/02
- [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction, Alistair Francis, 2021/09/02
  - Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction, Richard Henderson <=
  - Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction, Bin Meng, 2021/09/04
- [PATCH v1 2/2] target/riscv: Set mtval and stval support, Alistair Francis, 2021/09/02
  - Re: [PATCH v1 2/2] target/riscv: Set mtval and stval support, Richard Henderson, 2021/09/03
    - Re: [PATCH v1 2/2] target/riscv: Set mtval and stval support, Bin Meng, 2021/09/03