Re: [PATCH v1 2/2] target/riscv: Set mtval and stval support

qemu-devel

From:	Richard Henderson
Subject:	Re: [PATCH v1 2/2] target/riscv: Set mtval and stval support
Date:	Fri, 3 Sep 2021 19:05:57 +0200
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 9/3/21 1:23 AM, Alistair Francis wrote:

+    DEFINE_PROP_BOOL("mtval_inst", RISCVCPU, cfg.mtval_inst, true),


Dash not underscore for the prop name, I think.


r~

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[PATCH v1 0/2] RISC-V: Populate mtval and stval, Alistair Francis, 2021/09/02
- [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction, Alistair Francis, 2021/09/02
  - Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction, Richard Henderson, 2021/09/03
  - Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction, Bin Meng, 2021/09/04
- [PATCH v1 2/2] target/riscv: Set mtval and stval support, Alistair Francis, 2021/09/02
  - Re: [PATCH v1 2/2] target/riscv: Set mtval and stval support, Richard Henderson <=
    - Re: [PATCH v1 2/2] target/riscv: Set mtval and stval support, Bin Meng, 2021/09/03