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Re: [PATCH v2 06/22] target/riscv: Add AIA cpu feature
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v2 06/22] target/riscv: Add AIA cpu feature |
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Date: |
Sat, 4 Sep 2021 23:13:37 +0800 |
On Thu, Sep 2, 2021 at 7:51 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> We define a CPU feature for AIA CSR support in RISC-V CPUs which
> can be set by machine/device emulation. The RISC-V CSR emulation
> will also check this feature for emulating AIA CSRs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> target/riscv/cpu.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Re: [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts, (continued)
[PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2021/09/02
[PATCH v2 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 2021/09/02
[PATCH v2 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback, Anup Patel, 2021/09/02
[PATCH v2 09/22] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2021/09/02
[PATCH v2 06/22] target/riscv: Add AIA cpu feature, Anup Patel, 2021/09/02
[PATCH v2 07/22] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/09/02
[PATCH v2 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2021/09/02
[PATCH v2 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2021/09/02
[PATCH v2 12/22] target/riscv: Implement AIA interrupt filtering CSRs, Anup Patel, 2021/09/02
[PATCH v2 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2021/09/02
[PATCH v2 14/22] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2021/09/02
[PATCH v2 15/22] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2021/09/02
[PATCH v2 16/22] hw/riscv: virt: Use AIA INTC compatible string when available, Anup Patel, 2021/09/02