[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2 02/22] target/riscv: Implement SGEIP bit in hip and hie CS
|
From: |
Alistair Francis |
|
Subject: |
Re: [PATCH v2 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs |
|
Date: |
Wed, 15 Sep 2021 11:03:14 +1000 |
On Thu, Sep 2, 2021 at 9:40 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> A hypervsior can optionally take guest external interrupts using
> SGEIP bit of hip and hie CSRs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 3 ++-
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/csr.c | 18 +++++++++++-------
> 3 files changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index dc1353b858..9d97fbe3d9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -368,6 +368,7 @@ static void riscv_cpu_reset(DeviceState *dev)
> env->priv = PRV_M;
> env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
> env->mcause = 0;
> + env->miclaim = MIP_SGEIP;
> env->pc = env->resetvec;
> env->two_stage_lookup = false;
> #endif
> @@ -600,7 +601,7 @@ static void riscv_cpu_init(Object *obj)
> cpu_set_cpustate_pointers(cpu);
>
> #ifndef CONFIG_USER_ONLY
> - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
> + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
> #endif /* CONFIG_USER_ONLY */
> }
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 7330ff5a19..17ede1d4a9 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -504,6 +504,8 @@ typedef enum RISCVException {
> #define IRQ_S_EXT 9
> #define IRQ_VS_EXT 10
> #define IRQ_M_EXT 11
> +#define IRQ_S_GEXT 12
> +#define IRQ_LOCAL_MAX 13
>
> /* mip masks */
> #define MIP_USIP (1 << IRQ_U_SOFT)
> @@ -518,6 +520,7 @@ typedef enum RISCVException {
> #define MIP_SEIP (1 << IRQ_S_EXT)
> #define MIP_VSEIP (1 << IRQ_VS_EXT)
> #define MIP_MEIP (1 << IRQ_M_EXT)
> +#define MIP_SGEIP (1 << IRQ_S_GEXT)
>
> /* sip masks */
> #define SIP_SSIP MIP_SSIP
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 1f13d1042d..bc25c79e39 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -408,12 +408,13 @@ static RISCVException read_timeh(CPURISCVState *env,
> int csrno,
> #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
> #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
> #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
> +#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
>
> static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
> VS_MODE_INTERRUPTS;
> static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
> static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
> - VS_MODE_INTERRUPTS;
> + HS_MODE_INTERRUPTS;
> #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
> (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
> (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
> @@ -644,7 +645,7 @@ static RISCVException write_mideleg(CPURISCVState *env,
> int csrno,
> {
> env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
> if (riscv_has_ext(env, RVH)) {
> - env->mideleg |= VS_MODE_INTERRUPTS;
> + env->mideleg |= HS_MODE_INTERRUPTS;
> }
> return RISCV_EXCP_NONE;
> }
> @@ -660,6 +661,9 @@ static RISCVException write_mie(CPURISCVState *env, int
> csrno,
> target_ulong val)
> {
> env->mie = (env->mie & ~all_ints) | (val & all_ints);
> + if (!riscv_has_ext(env, RVH)) {
> + env->mie &= ~MIP_SGEIP;
> + }
> return RISCV_EXCP_NONE;
> }
>
> @@ -960,7 +964,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int
> csrno,
> }
>
> if (ret_value) {
> - *ret_value &= env->mideleg;
> + *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
> }
> return ret;
> }
> @@ -1078,7 +1082,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int
> csrno,
> write_mask & hvip_writable_mask);
>
> if (ret_value) {
> - *ret_value &= hvip_writable_mask;
> + *ret_value &= VS_MODE_INTERRUPTS;
> }
> return ret;
> }
> @@ -1091,7 +1095,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int
> csrno,
> write_mask & hip_writable_mask);
>
> if (ret_value) {
> - *ret_value &= hip_writable_mask;
> + *ret_value &= HS_MODE_INTERRUPTS;
> }
> return ret;
> }
> @@ -1099,14 +1103,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int
> csrno,
> static RISCVException read_hie(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> - *val = env->mie & VS_MODE_INTERRUPTS;
> + *val = env->mie & HS_MODE_INTERRUPTS;
> return RISCV_EXCP_NONE;
> }
>
> static RISCVException write_hie(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> - target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val &
> VS_MODE_INTERRUPTS);
> + target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val &
> HS_MODE_INTERRUPTS);
> return write_mie(env, CSR_MIE, newval);
> }
>
> --
> 2.25.1
>
>
- [PATCH v2 03/22] target/riscv: Implement hgeie and hgeip CSRs, (continued)
- [PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2021/09/02
- [PATCH v2 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 2021/09/02
- Re: [PATCH v2 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs,
Alistair Francis <=
- [PATCH v2 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback, Anup Patel, 2021/09/02
- [PATCH v2 09/22] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2021/09/02
- [PATCH v2 06/22] target/riscv: Add AIA cpu feature, Anup Patel, 2021/09/02
- [PATCH v2 07/22] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/09/02
- [PATCH v2 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2021/09/02
- [PATCH v2 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2021/09/02
- [PATCH v2 12/22] target/riscv: Implement AIA interrupt filtering CSRs, Anup Patel, 2021/09/02
- [PATCH v2 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2021/09/02