[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 05/12] escc: reset register values to zero in escc_reset()
From: |
Mark Cave-Ayland |
Subject: |
[PULL 05/12] escc: reset register values to zero in escc_reset() |
Date: |
Wed, 8 Sep 2021 12:54:44 +0100 |
This is to ensure that a device reset always returns the ESCC to a known state.
Note that this is currently redundant with the same code in escc_reset_chn()
but that will change shortly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-3-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/char/escc.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/char/escc.c b/hw/char/escc.c
index c87ecd59d8..b0d3b92dc1 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -300,9 +300,24 @@ static void escc_reset_chn(ESCCChannelState *s)
static void escc_reset(DeviceState *d)
{
ESCCState *s = ESCC(d);
+ int i, j;
- escc_reset_chn(&s->chn[0]);
- escc_reset_chn(&s->chn[1]);
+ for (i = 0; i < 2; i++) {
+ ESCCChannelState *cs = &s->chn[i];
+
+ /*
+ * According to the ESCC datasheet "Miscellaneous Questions" section
+ * on page 384, the values of the ESCC registers are not guaranteed on
+ * power-on until an explicit hardware or software reset has been
+ * issued. For now we zero the registers so that a device reset always
+ * returns the emulated device to a fixed state.
+ */
+ for (j = 0; j < ESCC_SERIAL_REGS; j++) {
+ cs->rregs[j] = 0;
+ cs->wregs[j] = 0;
+ }
+ escc_reset_chn(cs);
+ }
}
static inline void set_rxint(ESCCChannelState *s)
--
2.20.1
- [PULL 00/12] qemu-sparc queue 20210908, Mark Cave-Ayland, 2021/09/08
- [PULL 01/12] target/sparc: Drop use of gen_io_end(), Mark Cave-Ayland, 2021/09/08
- [PULL 02/12] tcg: Drop gen_io_end(), Mark Cave-Ayland, 2021/09/08
- [PULL 03/12] sun4m: fix setting CPU id when more than one CPU is present, Mark Cave-Ayland, 2021/09/08
- [PULL 04/12] escc: checkpatch fixes, Mark Cave-Ayland, 2021/09/08
- [PULL 05/12] escc: reset register values to zero in escc_reset(),
Mark Cave-Ayland <=
- [PULL 06/12] escc: introduce escc_soft_reset_chn() for software reset, Mark Cave-Ayland, 2021/09/08
- [PULL 07/12] escc: introduce escc_hard_reset_chn() for hardware reset, Mark Cave-Ayland, 2021/09/08
- [PULL 08/12] escc: implement soft reset as described in the datasheet, Mark Cave-Ayland, 2021/09/08
- [PULL 09/12] escc: implement hard reset as described in the datasheet, Mark Cave-Ayland, 2021/09/08
- [PULL 10/12] escc: remove register changes from escc_reset_chn(), Mark Cave-Ayland, 2021/09/08
- [PULL 11/12] escc: re-use escc_reset_chn() for soft reset, Mark Cave-Ayland, 2021/09/08
- [PULL 12/12] escc: fix STATUS_SYNC bit in R_STATUS register, Mark Cave-Ayland, 2021/09/08
- Re: [PULL 00/12] qemu-sparc queue 20210908, Peter Maydell, 2021/09/10