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[PULL 10/12] escc: remove register changes from escc_reset_chn()
From: |
Mark Cave-Ayland |
Subject: |
[PULL 10/12] escc: remove register changes from escc_reset_chn() |
Date: |
Wed, 8 Sep 2021 12:54:49 +0100 |
Now that register values at reset are handled elsewhere for all of device reset,
soft reset and hard reset, escc_reset_chn() only needs to handle initialisation
of internal device state.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-8-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/char/escc.c | 25 -------------------------
1 file changed, 25 deletions(-)
diff --git a/hw/char/escc.c b/hw/char/escc.c
index 80f1d1b8fc..22c97414a1 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -139,7 +139,6 @@
#define MISC2_PLLCMD0 0x20
#define MISC2_PLLCMD1 0x40
#define MISC2_PLLCMD2 0x80
-#define MISC2_PLLDIS 0x30
#define W_EXTINT 15
#define EXTINT_DCD 0x08
#define EXTINT_SYNCINT 0x10
@@ -279,31 +278,7 @@ static void escc_update_irq(ESCCChannelState *s)
static void escc_reset_chn(ESCCChannelState *s)
{
- int i;
-
s->reg = 0;
- for (i = 0; i < ESCC_SERIAL_REGS; i++) {
- s->rregs[i] = 0;
- s->wregs[i] = 0;
- }
- /* 1X divisor, 1 stop bit, no parity */
- s->wregs[W_TXCTRL1] = TXCTRL1_1STOP;
- s->wregs[W_MINTR] = MINTR_RST_ALL;
- /* Synch mode tx clock = TRxC */
- s->wregs[W_CLOCK] = CLOCK_TRXC;
- /* PLL disabled */
- s->wregs[W_MISC2] = MISC2_PLLDIS;
- /* Enable most interrupts */
- s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |
- EXTINT_TXUNDRN | EXTINT_BRKINT;
- if (s->disabled) {
- s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC |
- STATUS_CTS | STATUS_TXUNDRN;
- } else {
- s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN;
- }
- s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT;
-
s->rx = s->tx = 0;
s->rxint = s->txint = 0;
s->rxint_under_svc = s->txint_under_svc = 0;
--
2.20.1
- [PULL 00/12] qemu-sparc queue 20210908, Mark Cave-Ayland, 2021/09/08
- [PULL 01/12] target/sparc: Drop use of gen_io_end(), Mark Cave-Ayland, 2021/09/08
- [PULL 02/12] tcg: Drop gen_io_end(), Mark Cave-Ayland, 2021/09/08
- [PULL 03/12] sun4m: fix setting CPU id when more than one CPU is present, Mark Cave-Ayland, 2021/09/08
- [PULL 04/12] escc: checkpatch fixes, Mark Cave-Ayland, 2021/09/08
- [PULL 05/12] escc: reset register values to zero in escc_reset(), Mark Cave-Ayland, 2021/09/08
- [PULL 06/12] escc: introduce escc_soft_reset_chn() for software reset, Mark Cave-Ayland, 2021/09/08
- [PULL 07/12] escc: introduce escc_hard_reset_chn() for hardware reset, Mark Cave-Ayland, 2021/09/08
- [PULL 08/12] escc: implement soft reset as described in the datasheet, Mark Cave-Ayland, 2021/09/08
- [PULL 09/12] escc: implement hard reset as described in the datasheet, Mark Cave-Ayland, 2021/09/08
- [PULL 10/12] escc: remove register changes from escc_reset_chn(),
Mark Cave-Ayland <=
- [PULL 11/12] escc: re-use escc_reset_chn() for soft reset, Mark Cave-Ayland, 2021/09/08
- [PULL 12/12] escc: fix STATUS_SYNC bit in R_STATUS register, Mark Cave-Ayland, 2021/09/08
- Re: [PULL 00/12] qemu-sparc queue 20210908, Peter Maydell, 2021/09/10