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SMMU Stage 2 translation in QEMU
From: |
shashi . mallela |
Subject: |
SMMU Stage 2 translation in QEMU |
Date: |
Thu, 09 Sep 2021 16:17:40 -0400 |
Hi All,
I am trying to understand the approach required for an emulated SMMU to
convert IPAs(from each qemu guest) to PAs(respective host addresses)
using stage 2 tables.
The questions i have are:-
1) Since SMMU stage 2 tables are expected to be created and managed by
a hypervisor,if there is no kvm support,who is responsible to create
the stage 2 tables in host memory? is it even a valid use case to
consider smmu stage 2 support with no hypervisor present?
2) with SMMU emulated by qemu:-
a) who is responsible for hosting and programming the stage 2 table
base address registers?
b) what are the APIs available in qemu to access the stage 2 tables?
(will address_space_ API variants apply here?)
3) if each qemu instance (for a guest) emulates an SMMU,will there be a
need to protect concurrent access of stage 2 table(in host) by each of
the SMMUs?
Thanks
Shashi
- SMMU Stage 2 translation in QEMU,
shashi . mallela <=
- Re: SMMU Stage 2 translation in QEMU, Peter Maydell, 2021/09/10
- Re: SMMU Stage 2 translation in QEMU, shashi . mallela, 2021/09/10
- Re: SMMU Stage 2 translation in QEMU, Peter Maydell, 2021/09/10
- Re: SMMU Stage 2 translation in QEMU, shashi . mallela, 2021/09/10
- Re: SMMU Stage 2 translation in QEMU, Eric Auger, 2021/09/13
- Re: SMMU Stage 2 translation in QEMU, shashi . mallela, 2021/09/14
- Re: SMMU Stage 2 translation in QEMU, Eric Auger, 2021/09/15