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Re: SMMU Stage 2 translation in QEMU
From: |
shashi . mallela |
Subject: |
Re: SMMU Stage 2 translation in QEMU |
Date: |
Fri, 10 Sep 2021 08:39:50 -0400 |
I am referring to the latter,"purely emulated QEMU with an emulated
SMMU that handles accesses to emulated devices"
Thanks
Shashi
On Fri, 2021-09-10 at 10:25 +0100, Peter Maydell wrote:
> On Thu, 9 Sept 2021 at 21:18, <shashi.mallela@linaro.org> wrote:
> > I am trying to understand the approach required for an emulated
> > SMMU to
> > convert IPAs(from each qemu guest) to PAs(respective host
> > addresses)
> > using stage 2 tables.
> >
> > The questions i have are:-
> >
> > 1) Since SMMU stage 2 tables are expected to be created and managed
> > by
> > a hypervisor,if there is no kvm support,who is responsible to
> > create
> > the stage 2 tables in host memory? is it even a valid use case to
> > consider smmu stage 2 support with no hypervisor present?
>
> So what exactly is the use case you're talking about here?
> Do you mean "purely emulated QEMU, but using a host hardware
> IOMMU to do device passthrough of host devices to the guest"?
> Or do you mean "purely emulated QEMU with an emulated SMMU
> that handles accesses to emulated devices" ?
>
> thanks
> -- PMM
- SMMU Stage 2 translation in QEMU, shashi . mallela, 2021/09/09
- Re: SMMU Stage 2 translation in QEMU, Peter Maydell, 2021/09/10
- Re: SMMU Stage 2 translation in QEMU,
shashi . mallela <=
- Re: SMMU Stage 2 translation in QEMU, Peter Maydell, 2021/09/10
- Re: SMMU Stage 2 translation in QEMU, shashi . mallela, 2021/09/10
- Re: SMMU Stage 2 translation in QEMU, Eric Auger, 2021/09/13
- Re: SMMU Stage 2 translation in QEMU, shashi . mallela, 2021/09/14
- Re: SMMU Stage 2 translation in QEMU, Eric Auger, 2021/09/15